#define INTC_IPRH_INT58			(0x04000000)#define INTC_IPRH_INT57			(0x02000000)#define INTC_IPRH_INT56			(0x01000000)#define INTC_IPRH_INT55			(0x00800000)#define INTC_IPRH_INT54			(0x00400000)#define INTC_IPRH_INT53			(0x00200000)#define INTC_IPRH_INT52			(0x00100000)#define INTC_IPRH_INT51			(0x00080000)#define INTC_IPRH_INT50			(0x00040000)#define INTC_IPRH_INT49			(0x00020000)#define INTC_IPRH_INT48			(0x00010000)#define INTC_IPRH_INT47			(0x00008000)#define INTC_IPRH_INT46			(0x00004000)#define INTC_IPRH_INT45			(0x00002000)#define INTC_IPRH_INT44			(0x00001000)#define INTC_IPRH_INT43			(0x00000800)#define INTC_IPRH_INT42			(0x00000400)#define INTC_IPRH_INT41			(0x00000200)#define INTC_IPRH_INT40			(0x00000100)#define INTC_IPRH_INT39			(0x00000080)#define INTC_IPRH_INT38			(0x00000040)#define INTC_IPRH_INT37			(0x00000020)#define INTC_IPRH_INT36			(0x00000010)#define INTC_IPRH_INT35			(0x00000008)#define INTC_IPRH_INT34			(0x00000004)#define INTC_IPRH_INT33			(0x00000002)#define INTC_IPRH_INT32			(0x00000001)/* Bit definitions and macros for INTC_IPRL */#define INTC_IPRL_INT31			(0x80000000)#define INTC_IPRL_INT30			(0x40000000)#define INTC_IPRL_INT29			(0x20000000)#define INTC_IPRL_INT28			(0x10000000)#define INTC_IPRL_INT27			(0x08000000)#define INTC_IPRL_INT26			(0x04000000)#define INTC_IPRL_INT25			(0x02000000)#define INTC_IPRL_INT24			(0x01000000)#define INTC_IPRL_INT23			(0x00800000)#define INTC_IPRL_INT22			(0x00400000)#define INTC_IPRL_INT21			(0x00200000)#define INTC_IPRL_INT20			(0x00100000)#define INTC_IPRL_INT19			(0x00080000)#define INTC_IPRL_INT18			(0x00040000)#define INTC_IPRL_INT17			(0x00020000)#define INTC_IPRL_INT16			(0x00010000)#define INTC_IPRL_INT15			(0x00008000)#define INTC_IPRL_INT14			(0x00004000)#define INTC_IPRL_INT13			(0x00002000)#define INTC_IPRL_INT12			(0x00001000)#define INTC_IPRL_INT11			(0x00000800)#define INTC_IPRL_INT10			(0x00000400)#define INTC_IPRL_INT9			(0x00000200)#define INTC_IPRL_INT8			(0x00000100)#define INTC_IPRL_INT7			(0x00000080)#define INTC_IPRL_INT6			(0x00000040)#define INTC_IPRL_INT5			(0x00000020)#define INTC_IPRL_INT4			(0x00000010)#define INTC_IPRL_INT3			(0x00000008)#define INTC_IPRL_INT2			(0x00000004)#define INTC_IPRL_INT1			(0x00000002)#define INTC_IPRL_INT0			(0x00000001)/* Bit definitions and macros for INTC_ICONFIG */#define INTC_ICFG_ELVLPRI7		(0x8000)#define INTC_ICFG_ELVLPRI6		(0x4000)#define INTC_ICFG_ELVLPRI5		(0x2000)#define INTC_ICFG_ELVLPRI4		(0x1000)#define INTC_ICFG_ELVLPRI3		(0x0800)#define INTC_ICFG_ELVLPRI2		(0x0400)#define INTC_ICFG_ELVLPRI1		(0x0200)#define INTC_ICFG_EMASK			(0x0020)/* Bit definitions and macros for INTC_SIMR */#define INTC_SIMR_SALL			(0x40)#define INTC_SIMR_SIMR(x)		((x)&0x3F)/* Bit definitions and macros for INTC_CIMR */#define INTC_CIMR_CALL			(0x40)#define INTC_CIMR_CIMR(x)		((x)&0x3F)/* Bit definitions and macros for INTC_CLMASK */#define INTC_CLMASK_CLMASK(x)		((x)&0x0F)/* Bit definitions and macros for INTC_SLMASK */#define INTC_SLMASK_SLMASK(x)		((x)&0x0F)/* Bit definitions and macros for INTC_ICR */#define INTC_ICR_IL(x)			((x)&0x07)/********************************************************************** Queued Serial Peripheral Interface (QSPI)*********************************************************************//* Bit definitions and macros for QSPI_QMR */#define QSPI_QMR_MSTR			(0x8000)#define QSPI_QMR_DOHIE			(0x4000)#define QSPI_QMR_BITS(x)		(((x)&0x000F)<<10)#define QSPI_QMR_CPOL			(0x0200)#define QSPI_QMR_CPHA			(0x0100)#define QSPI_QMR_BAUD(x)		((x)&0x00FF)/* Bit definitions and macros for QSPI_QDLYR */#define QSPI_QDLYR_SPE			(0x8000)#define QSPI_QDLYR_QCD(x)		(((x)&0x007F)<<8)#define QSPI_QDLYR_DTL(x)		((x)&0x00FF)/* Bit definitions and macros for QSPI_QWR */#define QSPI_QWR_NEWQP(x)		((x)&0x000F)#define QSPI_QWR_ENDQP(x)		(((x)&0x000F)<<8)#define QSPI_QWR_CSIV			(0x1000)#define QSPI_QWR_WRTO			(0x2000)#define QSPI_QWR_WREN			(0x4000)#define QSPI_QWR_HALT			(0x8000)/* Bit definitions and macros for QSPI_QIR */#define QSPI_QIR_WCEFB			(0x8000)#define QSPI_QIR_ABRTB			(0x4000)#define QSPI_QIR_ABRTL			(0x1000)#define QSPI_QIR_WCEFE			(0x0800)#define QSPI_QIR_ABRTE			(0x0400)#define QSPI_QIR_SPIFE			(0x0100)#define QSPI_QIR_WCEF			(0x0008)#define QSPI_QIR_ABRT			(0x0004)#define QSPI_QIR_SPIF			(0x0001)/* Bit definitions and macros for QSPI_QAR */#define QSPI_QAR_ADDR(x)		((x)&0x003F)#define QSPI_QAR_TRANS			(0x0000)#define QSPI_QAR_RECV			(0x0010)#define QSPI_QAR_CMD			(0x0020)/* Bit definitions and macros for QSPI_QDR */#define QSPI_QDR_CONT			(0x8000)#define QSPI_QDR_BITSE			(0x4000)#define QSPI_QDR_DT			(0x2000)#define QSPI_QDR_DSCK			(0x1000)#define QSPI_QDR_QSPI_CS3		(0x0800)#define QSPI_QDR_QSPI_CS2		(0x0400)#define QSPI_QDR_QSPI_CS1		(0x0200)#define QSPI_QDR_QSPI_CS0		(0x0100)/********************************************************************** Pulse Width Modulation (PWM)*********************************************************************//* Bit definitions and macros for PWM_E */#define PWM_EN_PWME7			(0x80)#define PWM_EN_PWME5			(0x20)#define PWM_EN_PWME3			(0x08)#define PWM_EN_PWME1			(0x02)/* Bit definitions and macros for PWM_POL */#define PWM_POL_PPOL7			(0x80)#define PWM_POL_PPOL5			(0x20)#define PWM_POL_PPOL3			(0x08)#define PWM_POL_PPOL1			(0x02)/* Bit definitions and macros for PWM_CLK */#define PWM_CLK_PCLK7			(0x80)#define PWM_CLK_PCLK5			(0x20)#define PWM_CLK_PCLK3			(0x08)#define PWM_CLK_PCLK1			(0x02)/* Bit definitions and macros for PWM_PRCLK */#define PWM_PRCLK_PCKB(x)		(((x)&0x07)<<4)#define PWM_PRCLK_PCKA(x)		((x)&0x07)/* Bit definitions and macros for PWM_CAE */#define PWM_CAE_CAE7			(0x80)#define PWM_CAE_CAE5			(0x20)#define PWM_CAE_CAE3			(0x08)#define PWM_CAE_CAE1			(0x02)/* Bit definitions and macros for PWM_CTL */#define PWM_CTL_CON67			(0x80)#define PWM_CTL_CON45			(0x40)#define PWM_CTL_CON23			(0x20)#define PWM_CTL_CON01			(0x10)#define PWM_CTL_PSWAR			(0x08)#define PWM_CTL_PFRZ			(0x04)/* Bit definitions and macros for PWM_SDN */#define PWM_SDN_IF			(0x80)#define PWM_SDN_IE			(0x40)#define PWM_SDN_RESTART			(0x20)#define PWM_SDN_LVL			(0x10)#define PWM_SDN_PWM7IN			(0x04)#define PWM_SDN_PWM7IL			(0x02)#define PWM_SDN_SDNEN			(0x01)/********************************************************************** Watchdog Timer Modules (WTM)*********************************************************************//* Bit definitions and macros for WTM_WCR */#define WTM_WCR_WAIT			(0x0008)#define WTM_WCR_DOZE			(0x0004)#define WTM_WCR_HALTED			(0x0002)#define WTM_WCR_EN			(0x0001)/********************************************************************** Chip Configuration Module (CCM)*********************************************************************//* Bit definitions and macros for CCM_CCR */#define CCM_CCR_CSC(x)			(((x)&0x0003)<<8|0x0001)#define CCM_CCR_LIMP			(0x0041)#define CCM_CCR_LOAD			(0x0021)#define CCM_CCR_BOOTPS(x)		(((x)&0x0003)<<3|0x0001)#define CCM_CCR_OSC_MODE		(0x0005)#define CCM_CCR_PLL_MODE		(0x0003)#define CCM_CCR_RESERVED		(0x0001)/* Bit definitions and macros for CCM_RCON */#define CCM_RCON_CSC(x)			(((x)&0x0003)<<8|0x0001)#define CCM_RCON_LIMP			(0x0041)#define CCM_RCON_LOAD			(0x0021)#define CCM_RCON_BOOTPS(x)		(((x)&0x0003)<<3|0x0001)#define CCM_RCON_OSC_MODE		(0x0005)#define CCM_RCON_PLL_MODE		(0x0003)#define CCM_RCON_RESERVED		(0x0001)/* Bit definitions and macros for CCM_CIR */#define CCM_CIR_PIN(x)			(((x)&0x03FF)<<6)#define CCM_CIR_PRN(x)			((x)&0x003F)/* Bit definitions and macros for CCM_MISCCR */#define CCM_MISCCR_PLL_LOCK		(0x2000)#define CCM_MISCCR_LIMP			(0x1000)#define CCM_MISCCR_LCD_CHEN		(0x0100)#define CCM_MISCCR_SSI_PUE		(0x0080)#define CCM_MISCCR_SSI_PUS		(0x0040)#define CCM_MISCCR_TIM_DMA		(0x0020)#define CCM_MISCCR_SSI_SRC		(0x0010)#define CCM_MISCCR_USBDIV		(0x0002)#define CCM_MISCCR_USBSRC		(0x0001)/* Bit definitions and macros for CCM_CDR */#define CCM_CDR_LPDIV(x)		(((x)&0x000F)<<8)#define CCM_CDR_SSIDIV(x)		((x)&0x000F)/* Bit definitions and macros for CCM_UHCSR */#define CCM_UHCSR_PORTIND(x)		(((x)&0x0003)<<14)#define CCM_UHCSR_WKUP			(0x0004)#define CCM_UHCSR_UHMIE			(0x0002)#define CCM_UHCSR_XPDE			(0x0001)/* Bit definitions and macros for CCM_UOCSR */#define CCM_UOCSR_PORTIND(x)		(((x)&0x0003)<<14)#define CCM_UOCSR_DPPD			(0x2000)#define CCM_UOCSR_DMPD			(0x1000)#define CCM_UOCSR_DRV_VBUS		(0x0800)#define CCM_UOCSR_CRG_VBUS		(0x0400)#define CCM_UOCSR_DCR_VBUS		(0x0200)#define CCM_UOCSR_DPPU			(0x0100)#define CCM_UOCSR_AVLD			(0x0080)#define CCM_UOCSR_BVLD			(0x0040)#define CCM_UOCSR_VVLD			(0x0020)#define CCM_UOCSR_SEND			(0x0010)#define CCM_UOCSR_PWRFLT		(0x0008)#define CCM_UOCSR_WKUP			(0x0004)#define CCM_UOCSR_UOMIE			(0x0002)#define CCM_UOCSR_XPDE			(0x0001)/* not done yet *//********************************************************************** General Purpose I/O (GPIO)*********************************************************************//* Bit definitions and macros for GPIO_PODR_FECH_L */#define GPIO_PODR_FECH_L7		(0x80)#define GPIO_PODR_FECH_L6		(0x40)#define GPIO_PODR_FECH_L5		(0x20)#define GPIO_PODR_FECH_L4		(0x10)#define GPIO_PODR_FECH_L3		(0x08)#define GPIO_PODR_FECH_L2		(0x04)#define GPIO_PODR_FECH_L1		(0x02)#define GPIO_PODR_FECH_L0		(0x01)/* Bit definitions and macros for GPIO_PODR_SSI */#define GPIO_PODR_SSI_4			(0x10)#define GPIO_PODR_SSI_3			(0x08)#define GPIO_PODR_SSI_2			(0x04)#define GPIO_PODR_SSI_1			(0x02)#define GPIO_PODR_SSI_0			(0x01)/* Bit definitions and macros for GPIO_PODR_BUSCTL */#define GPIO_PODR_BUSCTL_3		(0x08)#define GPIO_PODR_BUSCTL_2		(0x04)#define GPIO_PODR_BUSCTL_1		(0x02)#define GPIO_PODR_BUSCTL_0		(0x01)/* Bit definitions and macros for GPIO_PODR_BE */#define GPIO_PODR_BE_3			(0x08)#define GPIO_PODR_BE_2			(0x04)#define GPIO_PODR_BE_1			(0x02)#define GPIO_PODR_BE_0			(0x01)/* Bit definitions and macros for GPIO_PODR_CS */#define GPIO_PODR_CS_5			(0x20)#define GPIO_PODR_CS_4			(0x10)#define GPIO_PODR_CS_3			(0x08)#define GPIO_PODR_CS_2			(0x04)#define GPIO_PODR_CS_1			(0x02)/* Bit definitions and macros for GPIO_PODR_PWM */#define GPIO_PODR_PWM_5			(0x20)#define GPIO_PODR_PWM_4			(0x10)#define GPIO_PODR_PWM_3			(0x08)#define GPIO_PODR_PWM_2			(0x04)/* Bit definitions and macros for GPIO_PODR_FECI2C */#define GPIO_PODR_FECI2C_3		(0x08)#define GPIO_PODR_FECI2C_2		(0x04)#define GPIO_PODR_FECI2C_1		(0x02)#define GPIO_PODR_FECI2C_0		(0x01)/* Bit definitions and macros for GPIO_PODR_UART */#define GPIO_PODR_UART_7		(0x80)#define GPIO_PODR_UART_6		(0x40)#define GPIO_PODR_UART_5		(0x20)#define GPIO_PODR_UART_4		(0x10)#define GPIO_PODR_UART_3		(0x08)#define GPIO_PODR_UART_2		(0x04)#define GPIO_PODR_UART_1		(0x02)#define GPIO_PODR_UART_0		(0x01)/* Bit definitions and macros for GPIO_PODR_QSPI */#define GPIO_PODR_QSPI_5		(0x20)#define GPIO_PODR_QSPI_4		(0x10)#define GPIO_PODR_QSPI_3		(0x08)#define GPIO_PODR_QSPI_2		(0x04)#define GPIO_PODR_QSPI_1		(0x02)#define GPIO_PODR_QSPI_0		(0x01)/* Bit definitions and macros for GPIO_PODR_TIMER */#define GPIO_PODR_TIMER_3		(0x08)#define GPIO_PODR_TIMER_2		(0x04)#define GPIO_PODR_TIMER_1		(0x02)#define GPIO_PODR_TIMER_0		(0x01)/* Bit definitions and macros for GPIO_PODR_LCDDATAH */#define GPIO_PODR_LCDDATAH_1		(0x02)#define GPIO_PODR_LCDDATAH_0		(0x01)/* Bit definitions and macros for GPIO_PODR_LCDDATAM */#define GPIO_PODR_LCDDATAM_7		(0x80)#define GPIO_PODR_LCDDATAM_6		(0x40)#define GPIO_PODR_LCDDATAM_5		(0x20)#define GPIO_PODR_LCDDATAM_4		(0x10)#define GPIO_PODR_LCDDATAM_3		(0x08)#define GPIO_PODR_LCDDATAM_2		(0x04)#define GPIO_PODR_LCDDATAM_1		(0x02)#define GPIO_PODR_LCDDATAM_0		(0x01)/* Bit definitions and macros for GPIO_PODR_LCDDATAL */#define GPIO_PODR_LCDDATAL_7		(0x80)#define GPIO_PODR_LCDDATAL_6		(0x40)#define GPIO_PODR_LCDDATAL_5		(0x20)#define GPIO_PODR_LCDDATAL_4		(0x10)#define GPIO_PODR_LCDDATAL_3		(0x08)#define GPIO_PODR_LCDDATAL_2		(0x04)#define GPIO_PODR_LCDDATAL_1		(0x02)#define GPIO_PODR_LCDDATAL_0		(0x01)/* Bit definitions and macros for GPIO_PODR_LCDCTLH */#define GPIO_PODR_LCDCTLH_0		(0x01)/* Bit definitions and macros for GPIO_PODR_LCDCTLL */#define GPIO_PODR_LCDCTLL_7		(0x80)#define GPIO_PODR_LCDCTLL_6		(0x40)#define GPIO_PODR_LCDCTLL_5		(0x20)#define GPIO_PODR_LCDCTLL_4		(0x10)#define GPIO_PODR_LCDCTLL_3		(0x08)#define GPIO_PODR_LCDCTLL_2		(0x04)#define GPIO_PODR_LCDCTLL_1		(0x02)#define GPIO_PODR_LCDCTLL_0		(0x01)/* Bit definitions and macros for GPIO_PDDR_FECH */#define GPIO_PDDR_FECH_L7		(0x80)#define GPIO_PDDR_FECH_L6		(0x40)#define GPIO_PDDR_FECH_L5		(0x20)#define GPIO_PDDR_FECH_L4		(0x10)#define GPIO_PDDR_FECH_L3		(0x08)#define GPIO_PDDR_FECH_L2		(0x04)#define GPIO_PDDR_FECH_L1		(0x02)#define GPIO_PDDR_FECH_L0		(0x01)/* Bit definitions and macros for GPIO_PDDR_SSI */#define GPIO_PDDR_SSI_4			(0x10)#define GPIO_PDDR_SSI_3			(0x08)#define GPIO_PDDR_SSI_2			(0x04)#define GPIO_PDDR_SSI_1			(0x02)#define GPIO_PDDR_SSI_0			(0x01)/* Bit definitions and macros for GPIO_PDDR_BUSCTL */#define GPIO_PDDR_BUSCTL_3		(0x08)#define GPIO_PDDR_BUSCTL_2		(0x04)#define GPIO_PDDR_BUSCTL_1		(0x02)#define GPIO_PDDR_BUSCTL_0		(0x01)/* Bit definitions and macros for GPIO_PDDR_BE */#define GPIO_PDDR_BE_3			(0x08)#define GPIO_PDDR_BE_2			(0x04)#define GPIO_PDDR_BE_1			(0x02)#define GPIO_PDDR_BE_0			(0x01)/* Bit definitions and macros for GPIO_PDDR_CS */#define GPIO_PDDR_CS_1			(0x02)#define GPIO_PDDR_CS_2			(0x04)#define GPIO_PDDR_CS_3			(0x08)#define GPIO_PDDR_CS_4			(0x10)#define GPIO_PDDR_CS_5			(0x20)/* Bit definitions and macros for GPIO_PDDR_PWM */#define GPIO_PDDR_PWM_2			(0x04)#define GPIO_PDDR_PWM_3			(0x08)#define GPIO_PDDR_PWM_4			(0x10)#define GPIO_PDDR_PWM_5			(0x20)/* Bit definitions and macros for GPIO_PDDR_FECI2C */#define GPIO_PDDR_FECI2C_0		(0x01)#define GPIO_PDDR_FECI2C_1		(0x02)#define GPIO_PDDR_FECI2C_2		(0x04)