/*******************************************************************
	ADSP-21065L EZ-LAB Evalutation Board
	   - SDRAM Interface Initialization
	   - Programmable I/O Flag LED Test
********************************************************************/
#include "def21065L.h"
#include "new65Ldefs.h"

#define sdram_size 0xfffff

.SEGMENT/DM segsdram;

.ENDSEG;

.SEGMENT/PM pm_code;

/*************************************************************************************
	Setup the SDRAM
	Assumes SDRAM part# MT48LC1M16A1TG-12 S
		SDCLK=60MHz
		tCK=15ns min @ CL=2	-> SDCL=2
		tRAS=72ns min		-> SDTRAS=5
		tRP=36ns min		-> SDTRP=3
		tREF=64ms/4K rows	-> SDRDIV=(2(30MHz)-CL-tRP-4)64ms/4096=937cycles

	2 SDRAMs by 16 bits wide total=1Mbitx32
	Mapped to MS3 addresses 0x03000000-0x030fffff
***************************************************************************************/
.GLOBAL 	Init_65L_SDRAM_Controller;
.GLOBAL 	Blink_LEDs_Test;

Init_65L_SDRAM_Controller:
		ustat1=dm(WAIT);
		bit clr ustat1 0x000f8000;	/*clear MS3 waitstate and mode*/
		dm(WAIT)=ustat1;

		ustat1=937;					/*refresh rate*/
		dm(SDRDIV)=ustat1;

		ustat1=dm(IOCTL);			/*mask in SDRAM settings*/
		bit set ustat1 SDPSS|SDBN2|SDBS3|SDTRP3|SDTRAS5|SDCL2|SDPGS256|SDDCK1;
		dm(IOCTL)=ustat1;
	      	rts;

/*-------------------------------------------------------------------------------------*/

Blink_LEDs_Test:
		/* Setup FLAG outputs */
		ustat1=dm(IOCTL);
		bit set ustat1 FLG4O|FLG5O|FLG6O|FLG7O|FLG8O|FLG9O;
		dm(IOCTL)=ustat1;		/*flag 5-9 are output*/
		ustat1=0x3f;			/*clear flags to start*/
		dm(IOSTAT)=ustat1;

		/* Blink flags 5 times */
		lcntr=10, do blink_loop until lce;
			lcntr=15000000;
			do delay until lce;
delay:			nop;

			ustat1=dm(IOSTAT);
			bit tgl ustat1 FLG4|FLG5|FLG6|FLG7|FLG8|FLG9;
blink_loop:	dm(IOSTAT)=ustat1;
		rts;
.ENDSEG;