Set user-defined property "IOSTANDARD =  DEFAULT" for instance <iobuf_13> in unit <system>.    Set user-defined property "SLEW =  SLOW" for instance <iobuf_13> in unit <system>.    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <iobuf_14> in unit <system>.    Set user-defined property "DRIVE =  12" for instance <iobuf_14> in unit <system>.    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <iobuf_14> in unit <system>.    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <iobuf_14> in unit <system>.    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <iobuf_14> in unit <system>.    Set user-defined property "SLEW =  SLOW" for instance <iobuf_14> in unit <system>.    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <iobuf_15> in unit <system>.    Set user-defined property "DRIVE =  12" for instance <iobuf_15> in unit <system>.    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <iobuf_15> in unit <system>.    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <iobuf_15> in unit <system>.    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <iobuf_15> in unit <system>.    Set user-defined property "SLEW =  SLOW" for instance <iobuf_15> in unit <system>.    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <iobuf_16> in unit <system>.    Set user-defined property "DRIVE =  12" for instance <iobuf_16> in unit <system>.    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <iobuf_16> in unit <system>.    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <iobuf_16> in unit <system>.    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <iobuf_16> in unit <system>.    Set user-defined property "SLEW =  SLOW" for instance <iobuf_16> in unit <system>.=========================================================================*                           HDL Synthesis                               *=========================================================================Performing bidirectional port resolution...Synthesizing Unit <system>.    Related source file is "../hdl/system.v".Unit <system> synthesized.=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================*                       Advanced HDL Synthesis                          *=========================================================================Loading device for application Rf_Device from file '2vp30.nph' in environment G:\Xilinx.Reading core <../implementation/ppc405_0_wrapper.ngc>.Reading core <../implementation/reset_block_wrapper.ngc>.Reading core <../implementation/plb_wrapper.ngc>.Reading core <../implementation/opb_wrapper.ngc>.Reading core <../implementation/plb2opb_wrapper.ngc>.Reading core <../implementation/rs232_uart_1_wrapper.ngc>.Reading core <../implementation/leds_4bit_wrapper.ngc>.Reading core <../implementation/dipsws_4bit_wrapper.ngc>.Reading core <../implementation/pushbuttons_5bit_wrapper.ngc>.Reading core <../implementation/ps2_ports_wrapper.ngc>.Reading core <../implementation/plb_bram_if_cntlr_1_wrapper.ngc>.Reading core <../implementation/plb_bram_if_cntlr_1_bram_wrapper.ngc>.Reading core <../implementation/ps2_ports_io_adapter_wrapper.ngc>.Reading core <../implementation/dcm_0_wrapper.ngc>.Reading core <../implementation/myfirewall_0_wrapper.ngc>.Loading core <ppc405_0_wrapper> for timing and area information for instance <ppc405_0>.Loading core <reset_block_wrapper> for timing and area information for instance <reset_block>.Loading core <plb_wrapper> for timing and area information for instance <plb>.Loading core <opb_wrapper> for timing and area information for instance <opb>.Loading core <plb2opb_wrapper> for timing and area information for instance <plb2opb>.Loading core <rs232_uart_1_wrapper> for timing and area information for instance <rs232_uart_1>.Loading core <leds_4bit_wrapper> for timing and area information for instance <leds_4bit>.Loading core <dipsws_4bit_wrapper> for timing and area information for instance <dipsws_4bit>.Loading core <pushbuttons_5bit_wrapper> for timing and area information for instance <pushbuttons_5bit>.Loading core <ps2_ports_wrapper> for timing and area information for instance <ps2_ports>.Loading core <plb_bram_if_cntlr_1_wrapper> for timing and area information for instance <plb_bram_if_cntlr_1>.Loading core <plb_bram_if_cntlr_1_bram_wrapper> for timing and area information for instance <plb_bram_if_cntlr_1_bram>.Loading core <ps2_ports_io_adapter_wrapper> for timing and area information for instance <ps2_ports_io_adapter>.Loading core <dcm_0_wrapper> for timing and area information for instance <dcm_0>.Loading core <myfirewall_0_wrapper> for timing and area information for instance <myfirewall_0>.=========================================================================Advanced HDL Synthesis ReportFound no macro==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <system> ...Mapping all equations...Building and optimizing final netlist ...INFO:Xst:2260 - The FF/Latch <plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_1> in Unit <plb> is equivalent to the following 2 FFs/Latches : <plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_1_1> <plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_1_2> INFO:Xst:2260 - The FF/Latch <plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_0> in Unit <plb> is equivalent to the following 2 FFs/Latches : <plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_0_1> <plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_0_2> INFO:Xst:2260 - The FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_19> in Unit <ps2_ports> is equivalent to the following FF/Latch : <ps2_ports/IPIF/Bus2IP_Addr_19_1> INFO:Xst:2260 - The FF/Latch <plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/sl_busy> in Unit <plb_bram_if_cntlr_1> is equivalent to the following FF/Latch : <plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/sl_busy_1> INFO:Xst:2260 - The FF/Latch <myfirewall_0/OPB_IPIF_I/OPB_BAM_I/opb_rnw_s0> in Unit <myfirewall_0> is equivalent to the following FF/Latch : <myfirewall_0/OPB_IPIF_I/OPB_BAM_I/opb_rnw_s0_1> INFO:Xst:2260 - The FF/Latch <plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_1> in Unit <plb> is equivalent to the following 2 FFs/Latches : <plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_1_1> <plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_1_2> INFO:Xst:2260 - The FF/Latch <plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_0> in Unit <plb> is equivalent to the following 2 FFs/Latches : <plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_0_1> <plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_0_2> INFO:Xst:2260 - The FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_19> in Unit <ps2_ports> is equivalent to the following FF/Latch : <ps2_ports/IPIF/Bus2IP_Addr_19_1> INFO:Xst:2260 - The FF/Latch <plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/sl_busy> in Unit <plb_bram_if_cntlr_1> is equivalent to the following FF/Latch : <plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/sl_busy_1> INFO:Xst:2260 - The FF/Latch <myfirewall_0/OPB_IPIF_I/OPB_BAM_I/opb_rnw_s0> in Unit <myfirewall_0> is equivalent to the following FF/Latch : <myfirewall_0/OPB_IPIF_I/OPB_BAM_I/opb_rnw_s0_1> PACKER Warning: Lut plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/Addr_cntr_load_en1 driving carry plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/GEN_SLOW_MODE_BURSTXFER.I_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/I_MUXCY can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.Final Macro Processing ...=========================================================================Final Register ReportFound no macro==================================================================================================================================================*                          Partition Report                             *=========================================================================Partition Implementation Status-------------------------------  No Partitions were found in this design.-------------------------------=========================================================================*                            Final Report                               *=========================================================================Final ResultsTop Level Output File Name         : ../implementation/system.ngcOutput Format                      : ngcOptimization Goal                  : speedKeep Hierarchy                     : noDesign Statistics# IOs                              : 72Cell Usage :# BELS                             : 2277#      GND                         : 14#      INV                         : 67#      LUT1                        : 77#      LUT2                        : 303#      LUT2_D                      : 10#      LUT2_L                      : 30#      LUT3                        : 322#      LUT3_D                      : 15#      LUT3_L                      : 28#      LUT4                        : 934#      LUT4_D                      : 32#      LUT4_L                      : 51#      MUXCY                       : 210#      MUXCY_L                     : 15#      MUXF5                       : 33#      MUXF6                       : 1#      VCC                         : 12#      XORCY                       : 123# FlipFlops/Latches                : 1554#      FD                          : 169#      FD_1                        : 5#      FDC                         : 57#      FDCE                        : 9#      FDCPE                       : 4#      FDE                         : 12#      FDP                         : 9#      FDPE                        : 7#      FDR                         : 564#      FDRE                        : 644#      FDRS                        : 21#      FDRSE                       : 21#      FDS                         : 21#      FDSE                        : 11# RAMS                             : 142#      RAM16X1D                    : 110