Entity <leds_4bit_wrapper> (Architecture <STRUCTURE>) compiled.=========================================================================*                     Design Hierarchy Analysis                         *=========================================================================Analyzing hierarchy for entity <leds_4bit_wrapper> in library <work> (architecture <STRUCTURE>).Analyzing hierarchy for entity <opb_gpio> in library <opb_gpio_v3_01_b> (architecture <imp>) with generics.	C_ALL_INPUTS = 0	C_ALL_INPUTS_2 = 0	C_BASEADDR = "01000000000000000000000000000000"	C_DOUT_DEFAULT = "00000000000000000000000000000000"	C_DOUT_DEFAULT_2 = "00000000000000000000000000000000"	C_FAMILY = "virtex2p"	C_GPIO_WIDTH = 4	C_HIGHADDR = "01000000000000001111111111111111"	C_INTERRUPT_PRESENT = 0	C_IS_BIDIR = 0	C_IS_BIDIR_2 = 1	C_IS_DUAL = 0	C_OPB_AWIDTH = 32	C_OPB_DWIDTH = 32	C_TRI_DEFAULT = "11111111111111111111111111111111"	C_TRI_DEFAULT_2 = "11111111111111111111111111111111"	C_USER_ID_CODE = 3Analyzing hierarchy for entity <opb_ipif> in library <opb_ipif_v3_01_a> (architecture <imp>) with generics.	C_ARD_DEPENDENT_PROPS_ARRAY = ((0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),	                               (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0))	C_ARD_ID_ARRAY = (100)	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000001000000000000000000000000000000",	                          "0000000000000000000000000000000001000000000000000000000000001111")	C_ARD_DWIDTH_ARRAY = (32)	C_PIPELINE_MODEL = 7	C_ARD_NUM_CE_ARRAY = (2)	C_OPB_DWIDTH = 32	C_IP_INTR_MODE_ARRAY = (5,5)	C_DEV_BURST_ENABLE = 0	C_DEV_BLK_ID = 0	C_INCLUDE_WR_BUF = 0	C_DEV_MIR_ENABLE = 0	C_OPB_AWIDTH = 32	C_INCLUDE_ADDR_CNTR = 0	C_FAMILY = "virtex2p"Analyzing hierarchy for entity <GPIO_Core> in library <opb_gpio_v3_01_b> (architecture <IMP>) with generics.	C_ALL_INPUTS_2 = false	C_ALL_INPUTS = false	C_DOUT_DEFAULT = "00000000000000000000000000000000"	C_DW = 32	C_GPIO_WIDTH = 4	C_DOUT_DEFAULT_2 = "00000000000000000000000000000000"	C_AW = 32	C_INTERRUPT_PRESENT = false	C_IS_BIDIR = false	C_IS_BIDIR_2 = true	C_IS_DUAL = false	C_OPB_DWIDTH = 32	C_TRI_DEFAULT = "11111111111111111111111111111111"	C_TRI_DEFAULT_2 = "11111111111111111111111111111111"Analyzing hierarchy for entity <opb_bam> in library <opb_ipif_v3_01_a> (architecture <implementation>) with generics.	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000001000000000000000000000000000000",	                          "0000000000000000000000000000000001000000000000000000000000001111")	C_ARD_DEPENDENT_PROPS_ARRAY = ((0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),	                               (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0))	C_ARD_DWIDTH_ARRAY = (32)	C_ARD_ID_ARRAY = (100)	C_ARD_NUM_CE_ARRAY = (2)	C_DEV_BLK_ID = 0	C_DEV_BURST_ENABLE = 0	C_DEV_MIR_ENABLE = 0	C_FAMILY = "virtex2p"	C_INCLUDE_ADDR_CNTR = 0	C_INCLUDE_WR_BUF = 0	C_IP_INTR_MODE_ARRAY = (5,5)	C_OPB_AWIDTH = 32	C_OPB_DWIDTH = 32	C_PIPELINE_MODEL = 7WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" line 262: VHDL Assertion Statement with non constant condition is ignored.WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" line 262: VHDL Assertion Statement with non constant condition is ignored.Analyzing hierarchy for entity <pselect> in library <proc_common_v2_00_a> (architecture <imp>) with generics.	C_AB = 28	C_AW = 32	C_BAR = "01000000000000000000000000000000"Analyzing hierarchy for entity <pselect> in library <proc_common_v2_00_a> (architecture <imp>) with generics.	C_AB = 0	C_AW = 4	C_BAR = "0000"Analyzing hierarchy for entity <pselect> in library <proc_common_v2_00_a> (architecture <imp>) with generics.	C_BAR = "0"	C_AW = 1	C_AB = 1Analyzing hierarchy for entity <pselect> in library <proc_common_v2_00_a> (architecture <imp>) with generics.	C_AW = 1	C_AB = 1	C_BAR = "1"Analyzing hierarchy for entity <IPIF_Steer> in library <proc_common_v2_00_a> (architecture <IMP>) with generics.	C_SMALLEST = 32	C_DWIDTH = 32	C_AWIDTH = 32Building hierarchy successfully finished.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <leds_4bit_wrapper> in library <work> (Architecture <STRUCTURE>).    Set user-defined property "X_CORE_INFO =  opb_gpio_v3_01_b" for unit <leds_4bit_wrapper>.WARNING:Xst:37 - Unknown property "IP_GROUP".    Set property "MAX_FANOUT = 10000" for signal <OPB_Clk> in unit <opb_gpio>.WARNING:Xst:37 - Unknown property "SIGIS".    Set property "MAX_FANOUT = 10000" for signal <OPB_Rst> in unit <opb_gpio>.WARNING:Xst:37 - Unknown property "SIGIS".WARNING:Xst:37 - Unknown property "SIGIS".WARNING:Xst:37 - Unknown property "IP_GROUP".Entity <leds_4bit_wrapper> analyzed. Unit <leds_4bit_wrapper> generated.Analyzing generic Entity <opb_gpio> in library <opb_gpio_v3_01_b> (Architecture <imp>).	C_TRI_DEFAULT_2 = "11111111111111111111111111111111"	C_ALL_INPUTS = 0	C_DOUT_DEFAULT_2 = "00000000000000000000000000000000"	C_DOUT_DEFAULT = "00000000000000000000000000000000"	C_BASEADDR = "01000000000000000000000000000000"	C_FAMILY = "virtex2p"	C_GPIO_WIDTH = 4	C_HIGHADDR = "01000000000000001111111111111111"	C_INTERRUPT_PRESENT = 0	C_IS_BIDIR_2 = 1	C_IS_DUAL = 0	C_IS_BIDIR = 0	C_OPB_AWIDTH = 32	C_OPB_DWIDTH = 32	C_USER_ID_CODE = 3	C_ALL_INPUTS_2 = 0	C_TRI_DEFAULT = "11111111111111111111111111111111"WARNING:Xst:37 - Unknown property "SIGIS".WARNING:Xst:37 - Unknown property "SIGIS".WARNING:Xst:37 - Unknown property "SIGIS".WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 402: Unconnected output port 'Bus2IP_CE' of component 'opb_ipif'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 402: Unconnected output port 'RFIFO2IP_AlmostFull' of component 'opb_ipif'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 402: Unconnected output port 'RFIFO2IP_Full' of component 'opb_ipif'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 402: Unconnected output port 'RFIFO2IP_Vacancy' of component 'opb_ipif'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 402: Unconnected output port 'RFIFO2IP_WrAck' of component 'opb_ipif'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 402: Unconnected output port 'WFIFO2IP_AlmostEmpty' of component 'opb_ipif'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 402: Unconnected output port 'WFIFO2IP_Data' of component 'opb_ipif'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 402: Unconnected output port 'WFIFO2IP_Empty' of component 'opb_ipif'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 402: Unconnected output port 'WFIFO2IP_Occupancy' of component 'opb_ipif'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 402: Unconnected output port 'WFIFO2IP_RdAck' of component 'opb_ipif'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 402: Unconnected output port 'Bus2IP_Freeze' of component 'opb_ipif'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 492: Unconnected output port 'GPIO_errAck' of component 'GPIO_Core'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 492: Unconnected output port 'GPIO_retry' of component 'GPIO_Core'.WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" line 492: Unconnected output port 'GPIO_toutSup' of component 'GPIO_Core'.Entity <opb_gpio> analyzed. Unit <opb_gpio> generated.Analyzing generic Entity <opb_ipif> in library <opb_ipif_v3_01_a> (Architecture <imp>).	C_OPB_DWIDTH = 32	C_PIPELINE_MODEL = 7	C_FAMILY = "virtex2p"	C_DEV_BURST_ENABLE = 0	C_INCLUDE_ADDR_CNTR = 0	C_ARD_NUM_CE_ARRAY = (2)	C_DEV_MIR_ENABLE = 0	C_ARD_DEPENDENT_PROPS_ARRAY = ((0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),	                               (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0))	C_ARD_ID_ARRAY = (100)	C_IP_INTR_MODE_ARRAY = (5,5)	C_OPB_AWIDTH = 32	C_ARD_DWIDTH_ARRAY = (32)	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000001000000000000000000000000000000",	                          "0000000000000000000000000000000001000000000000000000000000001111")	C_DEV_BLK_ID = 0	C_INCLUDE_WR_BUF = 0Entity <opb_ipif> analyzed. Unit <opb_ipif> generated.Analyzing generic Entity <opb_bam> in library <opb_ipif_v3_01_a> (Architecture <implementation>).	C_PIPELINE_MODEL = 7	C_OPB_DWIDTH = 32	C_IP_INTR_MODE_ARRAY = (5,5)