Release 8.2.02i - xst I.34Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.--> TABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) Design Hierarchy Analysis  4) HDL Analysis  5) HDL Synthesis     5.1) HDL Synthesis Report  6) Advanced HDL Synthesis     6.1) Advanced HDL Synthesis Report  7) Low Level Synthesis  8) Partition Report  9) Final Report     9.1) Device utilization summary     9.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput Format                       : MIXEDInput File Name                    : "plb_wrapper_xst.prj"---- Target ParametersTarget Device                      : xc2vp30ff896-7Output File Name                   : "../implementation/plb_wrapper.ngc"---- Source OptionsTop Module Name                    : plb_wrapper---- Target OptionsAdd IO Buffers                     : NO---- General OptionsOptimization Goal                  : speedOptimization Effort                : 1Hierarchy Separator                : /---- Other OptionsCores Search Directories           : {../implementation}==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_muxcy.vhd" in Library proc_common_v1_00_b.Entity <or_muxcy> compiled.Entity <or_muxcy> (Architecture <implementation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v1_00_b.Package <proc_common_pkg> compiled.WARNING:HDLParsers:3534 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" Line 364. In the function Get_RLOC_Name, not all control paths contain a return statement.WARNING:HDLParsers:3534 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" Line 379. In the function Get_Reg_File_Area, not all control paths contain a return statement.Package body <proc_common_pkg> compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd" in Library proc_common_v1_00_b.Entity <pselect> compiled.Entity <pselect> (Architecture <imp>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/down_counter.vhd" in Library proc_common_v1_00_b.Entity <down_counter> compiled.Entity <down_counter> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd" in Library proc_common_v1_00_b.Entity <mux_onehot> compiled.Entity <mux_onehot> (Architecture <imp>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_bits.vhd" in Library proc_common_v1_00_b.Entity <or_bits> compiled.Entity <or_bits> (Architecture <implementation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd" in Library proc_common_v1_00_b.Entity <or_gate> compiled.Entity <or_gate> (Architecture <imp>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/qual_priority.vhd" in Library plb_v34_v1_02_a.Entity <qual_priority> compiled.Entity <qual_priority> (Architecture <qual_priority>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/qual_request.vhd" in Library plb_v34_v1_02_a.Entity <qual_request> compiled.Entity <qual_request> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/bus_control.vhd" in Library plb_v34_v1_02_a.Entity <bus_control> compiled.Entity <bus_control> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/priority_encoder.vhd" in Library plb_v34_v1_02_a.Entity <priority_encoder> compiled.Entity <priority_encoder> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/pending_priority.vhd" in Library plb_v34_v1_02_a.Entity <pending_priority> compiled.Entity <pending_priority> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/pend_request.vhd" in Library plb_v34_v1_02_a.Entity <pend_request> compiled.Entity <pend_request> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/arb_addr_sel.vhd" in Library plb_v34_v1_02_a.Entity <arb_addr_sel> compiled.Entity <arb_addr_sel> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_priority_encoder.vhd" in Library plb_v34_v1_02_a.Entity <plb_priority_encoder> compiled.Entity <plb_priority_encoder> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/arb_control_sm.vhd" in Library plb_v34_v1_02_a.Entity <arb_control_sm> compiled.Entity <arb_control_sm> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/gen_qual_req.vhd" in Library plb_v34_v1_02_a.Entity <gen_qual_req> compiled.Entity <gen_qual_req> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/muxed_signals.vhd" in Library plb_v34_v1_02_a.Entity <muxed_signals> compiled.Entity <muxed_signals> (Architecture <implementation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/arb_registers.vhd" in Library plb_v34_v1_02_a.Entity <arb_registers> compiled.Entity <arb_registers> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/watchdog_timer.vhd" in Library plb_v34_v1_02_a.Entity <watchdog_timer> compiled.Entity <watchdog_timer> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/dcr_regs.vhd" in Library plb_v34_v1_02_a.Entity <dcr_regs> compiled.Entity <dcr_regs> (Architecture <implementation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_interrupt.vhd" in Library plb_v34_v1_02_a.Entity <plb_interrupt> compiled.Entity <plb_interrupt> (Architecture <plb_interrupt>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/bus_lock_sm.vhd" in Library plb_v34_v1_02_a.Entity <bus_lock_sm> compiled.Entity <bus_lock_sm> (Architecture <implementation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_addrpath.vhd" in Library plb_v34_v1_02_a.Entity <plb_addrpath> compiled.Entity <plb_addrpath> (Architecture <implementation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_wr_datapath.vhd" in Library plb_v34_v1_02_a.Entity <plb_wr_datapath> compiled.Entity <plb_wr_datapath> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_rd_datapath.vhd" in Library plb_v34_v1_02_a.Entity <plb_rd_datapath> compiled.Entity <plb_rd_datapath> (Architecture <simulation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_slave_ors.vhd" in Library plb_v34_v1_02_a.Entity <plb_slave_ors> compiled.Entity <plb_slave_ors> (Architecture <implementation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_arbiter_logic.vhd" in Library plb_v34_v1_02_a.Entity <plb_arbiter_logic> compiled.Entity <plb_arbiter_logic> (Architecture <implementation>) compiled.Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_v34.vhd" in Library plb_v34_v1_02_a.Entity <plb_v34> compiled.Entity <plb_v34> (Architecture <simulation>) compiled.Compiling vhdl file "C:/myproj2/firewall/myxps/hdl/plb_wrapper.vhd" in Library work.Entity <plb_wrapper> compiled.Entity <plb_wrapper> (Architecture <STRUCTURE>) compiled.=========================================================================*                     Design Hierarchy Analysis                         *=========================================================================Analyzing hierarchy for entity <plb_wrapper> in library <work> (architecture <STRUCTURE>).Analyzing hierarchy for entity <plb_v34> in library <plb_v34_v1_02_a> (architecture <simulation>) with generics.	C_BASEADDR = "1111111111"	C_DCR_AWIDTH = 10	C_DCR_DWIDTH = 32	C_DCR_INTFCE = 0	C_EXT_RESET_HIGH = 1	C_HIGHADDR = "0000000000"	C_IRQ_ACTIVE = '1'	C_NUM_OPBCLK_PLB2OPB_REARB = 5	C_PLB_AWIDTH = 32	C_PLB_DWIDTH = 64	C_PLB_MID_WIDTH = 1	C_PLB_NUM_MASTERS = 2	C_PLB_NUM_SLAVES = 2Analyzing hierarchy for entity <plb_addrpath> in library <plb_v34_v1_02_a> (architecture <implementation>) with generics.	C_PLB_AWIDTH = 32	C_PLB_DWIDTH = 64	C_NUM_MASTERS = 2Analyzing hierarchy for entity <plb_wr_datapath> in library <plb_v34_v1_02_a> (architecture <simulation>) with generics.	C_NUM_MASTERS = 2	C_PLB_DWIDTH = 64Analyzing hierarchy for entity <plb_rd_datapath> in library <plb_v34_v1_02_a> (architecture <simulation>) with generics.	C_NUM_MASTERS = 2	C_PLB_DWIDTH = 64Analyzing hierarchy for entity <plb_slave_ors> in library <plb_v34_v1_02_a> (architecture <implementation>) with generics.	C_NUM_MASTERS = 2	C_NUM_SLAVES = 2	C_PLB_DWIDTH = 64Analyzing hierarchy for entity <plb_arbiter_logic> in library <plb_v34_v1_02_a> (architecture <implementation>) with generics.	C_BASEADDR = "1111111111"	C_DCR_AWIDTH = 10	C_DCR_DWIDTH = 32	C_DCR_INTFCE = 0	C_HIGHADDR = "0000000000"	C_IRQ_ACTIVE = '1'	C_MID_BITS = 1	C_NUM_MASTERS = 2	C_NUM_OPBCLK_PLB2OPB_REARB = 5	C_NUM_PLB2OPB_BRIDGE = 2	C_PLB_AWIDTH = 32	C_PLB_DWIDTH = 64Analyzing hierarchy for entity <mux_onehot> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_DW = 32	C_NB = 2Analyzing hierarchy for entity <mux_onehot> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_DW = 8	C_NB = 2Analyzing hierarchy for entity <mux_onehot> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_NB = 2	C_DW = 4Analyzing hierarchy for entity <mux_onehot> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_NB = 2	C_DW = 3Analyzing hierarchy for entity <mux_onehot> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_DW = 1	C_NB = 2Analyzing hierarchy for entity <mux_onehot> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_DW = 2	C_NB = 2Analyzing hierarchy for entity <mux_onehot> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_DW = 64	C_NB = 2Analyzing hierarchy for entity <or_gate> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_USE_LUT_OR = true	C_OR_WIDTH = 2	C_BUS_WIDTH = 1Analyzing hierarchy for entity <or_gate> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_USE_LUT_OR = true	C_OR_WIDTH = 2	C_BUS_WIDTH = 2Analyzing hierarchy for entity <or_gate> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_OR_WIDTH = 2	C_BUS_WIDTH = 64	C_USE_LUT_OR = trueAnalyzing hierarchy for entity <or_gate> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_BUS_WIDTH = 4	C_OR_WIDTH = 2	C_USE_LUT_OR = trueAnalyzing hierarchy for entity <plb_priority_encoder> in library <plb_v34_v1_02_a> (architecture <simulation>) with generics.	C_NUM_MSTRS_PAD = 4	C_NUM_MASTERS = 2Analyzing hierarchy for entity <arb_control_sm> in library <plb_v34_v1_02_a> (architecture <simulation>) with generics.	C_NUM_MASTERS = 2	C_NUM_OPBCLK_PLB2OPB_REARB = 5	C_NUM_PLB2OPB_BRIDGE = 2Analyzing hierarchy for entity <gen_qual_req> in library <plb_v34_v1_02_a> (architecture <simulation>) with generics.	C_NUM_MASTERS = 2Analyzing hierarchy for entity <muxed_signals> in library <plb_v34_v1_02_a> (architecture <implementation>) with generics.	C_MID_BITS = 1	C_NUM_MASTERS = 2	C_NUM_MSTRS_PAD = 4WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.Analyzing hierarchy for entity <arb_registers> in library <plb_v34_v1_02_a> (architecture <simulation>) with generics.	C_NUM_MASTERS = 2Analyzing hierarchy for entity <watchdog_timer> in library <plb_v34_v1_02_a> (architecture <simulation>).Analyzing hierarchy for entity <plb_interrupt> in library <plb_v34_v1_02_a> (architecture <plb_interrupt>) with generics.	C_IRQ_ACTIVE = '1'Analyzing hierarchy for entity <bus_lock_sm> in library <plb_v34_v1_02_a> (architecture <implementation>).Analyzing hierarchy for entity <priority_encoder> in library <plb_v34_v1_02_a> (architecture <simulation>) with generics.	C_NUM_MASTERS = 4Analyzing hierarchy for entity <pending_priority> in library <plb_v34_v1_02_a> (architecture <simulation>) with generics.	C_NUM_MASTERS = 2Analyzing hierarchy for entity <pend_request> in library <plb_v34_v1_02_a> (architecture <simulation>) with generics.	C_NUM_MASTERS = 2Analyzing hierarchy for entity <arb_addr_sel> in library <plb_v34_v1_02_a> (architecture <simulation>) with generics.	C_NUM_MASTERS = 2Analyzing hierarchy for entity <mux_onehot> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_DW = 2	C_NB = 2Analyzing hierarchy for entity <mux_onehot> in library <proc_common_v1_00_b> (architecture <imp>) with generics.	C_DW = 1	C_NB = 2Analyzing hierarchy for entity <or_bits> in library <proc_common_v1_00_b> (architecture <implementation>) with generics.	C_BUS_SIZE = 4	C_NUM_BITS = 2	C_START_BIT = 2Analyzing hierarchy for entity <or_bits> in library <proc_common_v1_00_b> (architecture <implementation>) with generics.	C_NUM_BITS = 1	C_START_BIT = 1	C_BUS_SIZE = 4Analyzing hierarchy for entity <or_bits> in library <proc_common_v1_00_b> (architecture <implementation>) with generics.