.ALIASES
R_R1            R1(1=N712192 2=ERR ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS816272@ANALOG.R.Normal(chips)
C_C1            C1(1=ERR 2=N8148361 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS814826@ANALOG.C.Normal(chips)
V_Vstim          Vstim(+=N711682 -=0 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS815070@SOURCE.VAC.Normal(chips)
V_Vref          Vref(+=N712414 -=0 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS816290@SOURCE.VDC.Normal(chips)
X_U10           U10(1=N712414 5=N712198 7=ERR ) CN @CHAPTER 2_1.test buck open-loop
+CM(sch_1):INS814842@APPLICATION.AMPSIMP.Normal(chips)
X_U11           U11(A=N712322 C=N712726 P=0 VC=N712694 DC=DUTY ) CN @CHAPTER 2_1.test buck open-loop
+CM(sch_1):INS815092@PWMSWITCH.PWMCM.Normal(chips)
V_V8            V8(+=N711732 -=0 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS816310@SOURCE.VDC.Normal(chips)
R_Resr          Resr(1=N712348 2=VOUT ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS814876@ANALOG.R.Normal(chips)
V_V7            V7(+=N711720 -=0 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS816332@SOURCE.VDC.Normal(chips)
R_Rload          Rload(1=0 2=VOUT ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS815134@ANALOG.R.Normal(chips)
R_Rupper          Rupper(1=N712198 2=VOUT ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS814896@ANALOG.R.Normal(chips)
C_C2            C2(1=ERR 2=N712198 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS816352@ANALOG.C.Normal(chips)
R_R5            R5(1=N712726 2=N8150401 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS815154@ANALOG.R.Normal(chips)
C_COL           COL(1=N712694 2=N711682 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS814916@ANALOG.C.Normal(chips)
V_Vin           Vin(+=N712322 -=0 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS816368@SOURCE.VDC.Normal(chips)
R_R2            R2(1=N8148361 2=N712198 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS814932@ANALOG.R.Normal(chips)
V_V9            V9(+=N711726 -=0 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS814952@SOURCE.VDC.Normal(chips)
C_Cout          Cout(1=0 2=N712348 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS814974@ANALOG.C.Normal(chips)
R_Rdummy          Rdummy(1=0 2=DUTY ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS814990@ANALOG.R.Normal(chips)
L_LOL           LOL(1=N712192 2=N712694 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS814760@ANALOG.L.Normal(chips)
R_Rlower          Rlower(1=0 2=N712198 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS815010@ANALOG.R.Normal(chips)
R_R22           R22(1=N711732 2=0 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS814782@ANALOG.R.Normal(chips)
L_L1            L1(1=VOUT 2=N8150401 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS815030@ANALOG.L.Normal(chips)
R_R25           R25(1=N711726 2=0 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS814804@ANALOG.R.Normal(chips)
R_R26           R26(1=N711720 2=0 ) CN @CHAPTER 2_1.test buck open-loop CM(sch_1):INS815050@ANALOG.R.Normal(chips)
_    _(vout=VOUT)
_    _(duty=DUTY)
_    _(err=ERR)
.ENDALIASES