#include "main.h"

//---------------spi interface initialize----------------------------
void SPI_Initialize()
{   
	while (!(P3IN & 0x08));              // If clock sig from mstr stays low,
                                         // it is not yet in SPI mode
	P3SEL |= BIT1 + BIT2 + BIT3;         // P3.1,3.2,3.3 UCB0SIMO,UCB0SOMI,UCBOCLK option select
	UCB0CTL1 |= UCSWRST;                 // Disable USCI first
	UCB0CTL0 |= UCCKPL + UCMSB + UCSYNC; // 3-pin, 8-bit SPI slave
	UCB0CTL1 &= ~UCSWRST;    
	//IE2 |= UCB0RXIE;
	//__bis_SR_register(LPM4_bits + GIE);       // Enter LPM4, enable interrupts
}

//---------------initialize system clock-----------------------------
void OSCsel(void)
{
    unsigned int ii1;

    BCSCTL1 |= XTS + XT2OFF;                       // ACLK = LFXT1 HF XTAL
    BCSCTL3 |= LFXT1S1;                       // 3 ?16MHz crystal or resonator
		
    do
    {
      	IFG1 &= ~OFIFG;                   // Clear OSCFault flag
      	for (ii1 = 0xFF; ii1 > 0; ii1--); // Time delay for flag to set
    }
    while ((IFG1 & OFIFG) == OFIFG);    // OSCFault flag still set?
    BCSCTL2 |= SELM1 + SELM0 + SELS;    //  MCLK = SMCLK = HF LFXT1 (safe)
}

//---------------delay(using DCO)---------------------------------------
void delay_ms(unsigned int n_ms)
{
    unsigned int ii1, ii0;
    for(ii0=n_ms; ii0>0; ii0--) 
	{
        ii1 = 0x07FF;                    // Delay
        do (ii1--);
        while (ii1 != 0);
    }
}

//---------------initialize system--------------------------------------
void Initialize(void)
{
	WDTCTL = WDTPW + WDTHOLD;
	SPI_Initialize();

	EN_Set;
	TRFDisable;
	delay_ms(1);
	TRFEnable;
	delay_ms(1);

	PARset(); 
	
        LED_Set;
        
    SetTRF();
    InitialTRF7960();
    OSCsel();
    EnableInterrupts; 
}

//---------------SPI send 1 byte data------------------------------------
void Put_byte(unsigned char abyte)
{
	//SlaveSelectLOW;
	UCB0TXBUF = abyte;
	//SlaveSelectHIGH;

}

//---------------operate the interrupt data------------------------------
void InterruptHandlerReader(unsigned char *Register)
{   
	if(*Register == 0xA0)// TX active and only 3 bytes left in FIFO 
		i_reg = 0x00;

	else if(*Register == BIT7)//no response interrupt
	{					/* TX complete */
		i_reg = 0x00;
		*Register = Reset;			/* reset the FIFO after TX */
		DirectCommand(Register);
    }	
 
 	else if(*Register == BIT6)
	{	/* RX flag means that EOF has been recieved */
		/* and the number of unread bytes is in FIFOstatus regiter */
		if(RXErrorFlag == 0x02)
		{
			i_reg = 0x02;
			return;
		}

		*Register = FIFOStatus;
		ReadSingle(Register, 1);					/* determine the number of bytes left in FIFO */
//                ReadCont(Register, 1);	
		*Register = (0x0F &*Register) + 0x01;
		buf[RXTXstate] = FIFO;			/* write the recieved bytes to the correct place of the*/
													
												
		ReadCont(&buf[RXTXstate], *Register);
		RXTXstate = RXTXstate +*Register;

		*Register = TXLenghtByte2;					/* determine if there are broken bytes */
	 //       ReadSingle(Register, 1);					/* determine the number of bits */
                  ReadCont(Register, 1);

		if((*Register & BIT0) == BIT0)
		{
			*Register = (*Register >> 1) & 0x07;	/* mask the first 5 bits */
			*Register = 8 -*Register;
			buf[RXTXstate - 1] &= 0xFF << *Register;
		}								/* if */


		*Register = Reset;				/* reset the FIFO after last byte has been read out */
		DirectCommand(Register);

		i_reg = 0xFF;					/* signal to the recieve funnction that this are the last bytes */
	}   

	else if(*Register & 0x60)
	{
        buf[RXTXstate] = FIFO;
		ReadCont(&buf[RXTXstate], 9);
		RXTXstate = RXTXstate + 9;

		if(irqPORT & irqPIN)
		{
			*Register = IRQStatus;
			ReadSingle(Register, 1);
			irqCLR;

			if(*Register == 0x40)
			{
				*Register = FIFOStatus;
				ReadSingle(Register, 1);
				*Register = 0x0F & (*Register + 0x01);//indicates how many bytes are loaded in FIFO were not read out yet
				buf[RXTXstate] = FIFO;

				ReadCont(&buf[RXTXstate], *Register);//read out the left bytes
				RXTXstate = RXTXstate + *Register;

				*Register = TXLenghtByte2;					/* determine if there are broken bytes */
				ReadSingle(Register, 1);					/* determine the number of bits */

				if((*Register & BIT0) == BIT0)
				{
					*Register = (*Register >> 1) & 0x07;	/* mask the first 5 bits */
					*Register = 8 -*Register;
					buf[RXTXstate - 1] &= 0xFF << *Register;
				}

				i_reg = 0xFF;			/* signal to the recieve funnction that this are the last bytes */
				*Register = Reset;		/* reset the FIFO after last byte has been read out */
				DirectCommand(Register);
			}
			else if(*Register == 0x50)
				i_reg = 0x02;
		}

		else
		{
			IrqReset();
			if(Register[0] == 0x00) //receive end
			i_reg = 0xFF;
		}
	}

	else if((*Register & BIT4) == BIT4)//CRC error
	{
		if((*Register & BIT5) == BIT5)
		{
			i_reg = 0x01;	/* RX active */
			RXErrorFlag = 0x02;
		}
		else
			i_reg = 0x02;
	}

	else if((*Register & BIT2) == BIT2)//Byte framing or EOF error
	{
		if((*Register & BIT5) == BIT5)
		{
			i_reg = 0x01;	/* RX active */
			RXErrorFlag = 0x02;
		}
		else
			i_reg = 0x02;
	}

	else if(*Register == BIT0)							/* No response interrupt */
		i_reg = 0x00;
	
	else
	{						/* Interrupt register not properly set */
		i_reg = 0x02;

		*Register = StopDecoders;	/* reset the FIFO after TX */
		DirectCommand(Register);

		*Register = Reset;
		DirectCommand(Register);

		IrqReset();
     	
		irqCLR;
	}
}


//-------------------external interrupt--------------------------------------
#pragma vector = PORT2_VECTOR
__interrupt void Port_B (void)		/* interrupt handler */
{
	unsigned char Register[4];
					
	do
	{
		irqCLR;						/* PORT2 interrupt flag clear */
		Register[0] = IRQStatus;
		Register[1] = IRQMask;
		ReadCont(Register, 2);
		if(*Register == 0xA0)
			__low_power_mode_off_on_exit();
             
		InterruptHandlerReader(&Register[0]);				
	}
	while((irqPORT & irqPIN) == irqPIN);
}

//----------------parallel interface initialize------------------------------
void PARset(void)
{
	EN_Set;
	TRFDirOUT;			/* P4 output */
	TRFFunc;
	TRFWrite = 0x00;	/* P4 set to 0 - choose parallel inteface for the TRF796x */

	clkOFF;
	clkPOUTset;			/* DATA_CLK on P1.2 */

	irqPINset;
	irqEDGEset;			/* rising edge interrupt */
}