-- Xilinx Vhdl produced by program ngd2vhdl F.23-- Command: -rpw 100 -ar Structure -xon false -w -log __projnav/ngd2vhdl.log spi_master.nga spi_master_timesim.vhd -- Input file: spi_master.nga-- Output file: spi_master_timesim.vhd-- Design name: spi_master-- Xilinx: C:/Xilinx_webpack_51-- # of Entities: 1-- Device: XCR3256XL-7-TQ144-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,-- or used in any other manner other than simulation. This netlist uses simulation-- primitives which may not represent the true implementation of the device, however-- the netlist is functionally correct. Do not modify this file.-- Model for  ROC (Reset-On-Configuration) Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity ROC is  generic (InstancePath: STRING := "*";           WIDTH : Time := 100 ns);  port(O : out std_ulogic := '1') ;  attribute VITAL_LEVEL0 of ROC : entity is TRUE;end ROC;architecture ROC_V of ROC isattribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;begin  ONE_SHOT : process  begin    if (WIDTH <= 0 ns) then       assert FALSE report       "*** Error: a positive value of WIDTH must be specified ***"       severity failure;    else       wait for WIDTH;       O <= '0';    end if;    wait;  end process ONE_SHOT;end ROC_V;library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SIMPRIM;use SIMPRIM.VCOMPONENTS.ALL;use SIMPRIM.VPACKAGE.ALL;entity spi_master is  port (    rd_n : in STD_LOGIC := 'X';     wr_n : in STD_LOGIC := 'X';     ale_n : in STD_LOGIC := 'X';     psen_n : in STD_LOGIC := 'X';     clk : in STD_LOGIC := 'X';     reset : in STD_LOGIC := 'X';     ss_in_n : in STD_LOGIC := 'X';     miso : in STD_LOGIC := 'X';     sck : inout STD_LOGIC;     int_n : out STD_LOGIC;     mosi : out STD_LOGIC;     rcv_full : out STD_LOGIC;     xmit_empty : out STD_LOGIC;     addr : in STD_LOGIC_VECTOR ( 7 downto 0 );     addr_data : inout STD_LOGIC_VECTOR ( 7 downto 0 );     ss_n : out STD_LOGIC_VECTOR ( 7 downto 0 )   );end spi_master;architecture Structure of spi_master is  component ROC    generic (InstancePath: STRING := "*";             WIDTH : Time := 100 ns);    port (O : out STD_ULOGIC := '1');  end component;  signal addr_data_0_MC_Q : STD_LOGIC;   signal addr_data_0_MC_OE : STD_LOGIC;   signal addr_data_0_MC_Q_tsim_ireg_Q : STD_LOGIC;   signal FOOBAR5_ctinst_7 : STD_LOGIC;   signal addr_data_0_MC_R_OR_PRLD : STD_LOGIC;   signal addr_data_0_MC_D : STD_LOGIC;   signal clk_II_FCLK : STD_LOGIC;   signal reset_II_UIM : STD_LOGIC;   signal FOOBAR5_ctinst_0 : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_int : STD_LOGIC;   signal uc_intrface_spierr_reset : STD_LOGIC;   signal FOOBAR5_ctinst_4 : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_int_MC_Q : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_int_MC_D : STD_LOGIC;   signal FOOBAR4_ctinst_7 : STD_LOGIC;   signal rd_n_II_UIM : STD_LOGIC;   signal uc_intrface_prs_state_fft1 : STD_LOGIC;   signal uc_intrface_prs_state_fft2 : STD_LOGIC;   signal FOOBAR4_ctinst_0 : STD_LOGIC;   signal uc_intrface_spien : STD_LOGIC;   signal uc_intrface_prs_state_fft1_MC_Q : STD_LOGIC;   signal uc_intrface_prs_state_fft1_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_prs_state_fft1_MC_D : STD_LOGIC;   signal uc_intrface_prs_state_fft1_MC_D1 : STD_LOGIC;   signal uc_intrface_address_match : STD_LOGIC;   signal uc_intrface_prs_state_fft1_MC_D2_PT_0 : STD_LOGIC;   signal wr_n_II_UIM : STD_LOGIC;   signal uc_intrface_prs_state_fft1_MC_D2_PT_1 : STD_LOGIC;   signal ale_n_II_UIM : STD_LOGIC;   signal psen_n_II_UIM : STD_LOGIC;   signal uc_intrface_prs_state_fft1_MC_D2_PT_2 : STD_LOGIC;   signal uc_intrface_prs_state_fft1_MC_D2 : STD_LOGIC;   signal uc_intrface_prs_state_fft1_MC_D_TFF : STD_LOGIC;   signal uc_intrface_prs_state_fft2_MC_Q : STD_LOGIC;   signal uc_intrface_prs_state_fft2_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_prs_state_fft2_MC_D : STD_LOGIC;   signal uc_intrface_prs_state_fft2_MC_D1 : STD_LOGIC;   signal uc_intrface_prs_state_fft2_MC_D2_PT_0 : STD_LOGIC;   signal uc_intrface_prs_state_fft2_MC_D2_PT_1 : STD_LOGIC;   signal uc_intrface_prs_state_fft2_MC_D2_PT_2 : STD_LOGIC;   signal uc_intrface_prs_state_fft2_MC_D2 : STD_LOGIC;   signal uc_intrface_prs_state_fft2_MC_D_TFF : STD_LOGIC;   signal ale_n_II_FCLK : STD_LOGIC;   signal uc_intrface_address_match_MC_Q : STD_LOGIC;   signal uc_intrface_address_match_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_address_match_MC_D : STD_LOGIC;   signal addr_0_II_UIM : STD_LOGIC;   signal addr_1_II_UIM : STD_LOGIC;   signal addr_2_II_UIM : STD_LOGIC;   signal addr_3_II_UIM : STD_LOGIC;   signal addr_4_II_UIM : STD_LOGIC;   signal addr_5_II_UIM : STD_LOGIC;   signal addr_6_II_UIM : STD_LOGIC;   signal addr_7_II_UIM : STD_LOGIC;   signal uc_intrface_address_match_MC_D1_PT_0 : STD_LOGIC;   signal uc_intrface_address_match_MC_D1 : STD_LOGIC;   signal uc_intrface_address_match_MC_D2 : STD_LOGIC;   signal uc_intrface_spien_MC_Q : STD_LOGIC;   signal uc_intrface_spien_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_spien_MC_D : STD_LOGIC;   signal uc_intrface_spien_MC_D1 : STD_LOGIC;   signal uc_intrface_cntrl_en : STD_LOGIC;   signal addr_data_7_II_UIM : STD_LOGIC;   signal uc_intrface_spien_MC_D2_PT_0 : STD_LOGIC;   signal uc_intrface_spien_MC_D2_PT_1 : STD_LOGIC;   signal uc_intrface_spien_MC_D2 : STD_LOGIC;   signal uc_intrface_spien_MC_D_TFF : STD_LOGIC;   signal uc_intrface_cntrl_en_MC_Q : STD_LOGIC;   signal uc_intrface_cntrl_en_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_cntrl_en_MC_D : STD_LOGIC;   signal uc_intrface_cntrl_en_MC_D1_PT_0 : STD_LOGIC;   signal uc_intrface_cntrl_en_MC_D1 : STD_LOGIC;   signal uc_intrface_cntrl_en_MC_D2 : STD_LOGIC;   signal uc_intrface_address_low_0_MC_Q : STD_LOGIC;   signal uc_intrface_address_low_0_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_address_low_0_MC_D : STD_LOGIC;   signal ale_n_II_FCLK_tsimcreated_inv_Q : STD_LOGIC;   signal addr_data_0_II_UIM : STD_LOGIC;   signal uc_intrface_address_low_0_MC_D1_PT_0 : STD_LOGIC;   signal uc_intrface_address_low_0_MC_D1 : STD_LOGIC;   signal uc_intrface_address_low_0_MC_D2 : STD_LOGIC;   signal uc_intrface_address_low_1_MC_Q : STD_LOGIC;   signal uc_intrface_address_low_1_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_address_low_1_MC_D : STD_LOGIC;   signal addr_data_1_II_UIM : STD_LOGIC;   signal uc_intrface_address_low_1_MC_D1_PT_0 : STD_LOGIC;   signal uc_intrface_address_low_1_MC_D1 : STD_LOGIC;   signal uc_intrface_address_low_1_MC_D2 : STD_LOGIC;   signal uc_intrface_address_low_2_MC_Q : STD_LOGIC;   signal uc_intrface_address_low_2_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_address_low_2_MC_D : STD_LOGIC;   signal addr_data_2_II_UIM : STD_LOGIC;   signal uc_intrface_address_low_2_MC_D1_PT_0 : STD_LOGIC;   signal uc_intrface_address_low_2_MC_D1 : STD_LOGIC;   signal uc_intrface_address_low_2_MC_D2 : STD_LOGIC;   signal uc_intrface_address_low_3_MC_Q : STD_LOGIC;   signal uc_intrface_address_low_3_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_address_low_3_MC_D : STD_LOGIC;   signal addr_data_3_II_UIM : STD_LOGIC;   signal uc_intrface_address_low_3_MC_D1_PT_0 : STD_LOGIC;   signal uc_intrface_address_low_3_MC_D1 : STD_LOGIC;   signal uc_intrface_address_low_3_MC_D2 : STD_LOGIC;   signal uc_intrface_address_low_4_MC_Q : STD_LOGIC;   signal uc_intrface_address_low_4_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_address_low_4_MC_D : STD_LOGIC;   signal addr_data_4_II_UIM : STD_LOGIC;   signal uc_intrface_address_low_4_MC_D1_PT_0 : STD_LOGIC;   signal uc_intrface_address_low_4_MC_D1 : STD_LOGIC;   signal uc_intrface_address_low_4_MC_D2 : STD_LOGIC;   signal uc_intrface_address_low_5_MC_Q : STD_LOGIC;   signal uc_intrface_address_low_5_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_address_low_5_MC_D : STD_LOGIC;   signal addr_data_5_II_UIM : STD_LOGIC;   signal uc_intrface_address_low_5_MC_D1_PT_0 : STD_LOGIC;   signal uc_intrface_address_low_5_MC_D1 : STD_LOGIC;   signal uc_intrface_address_low_5_MC_D2 : STD_LOGIC;   signal uc_intrface_address_low_6_MC_Q : STD_LOGIC;   signal uc_intrface_address_low_6_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_address_low_6_MC_D : STD_LOGIC;   signal addr_data_6_II_UIM : STD_LOGIC;   signal uc_intrface_address_low_6_MC_D1_PT_0 : STD_LOGIC;   signal uc_intrface_address_low_6_MC_D1 : STD_LOGIC;   signal uc_intrface_address_low_6_MC_D2 : STD_LOGIC;   signal uc_intrface_address_low_7_MC_Q : STD_LOGIC;   signal uc_intrface_address_low_7_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_address_low_7_MC_D : STD_LOGIC;   signal uc_intrface_address_low_7_MC_D1_PT_0 : STD_LOGIC;   signal uc_intrface_address_low_7_MC_D1 : STD_LOGIC;   signal uc_intrface_address_low_7_MC_D2 : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_neg : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_pos : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_int_MC_D1_PT_0 : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_int_MC_D1 : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_int_MC_D2 : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_neg_MC_Q : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_neg_MC_D : STD_LOGIC;   signal clk_II_FCLK_tsimcreated_inv_Q : STD_LOGIC;   signal ss_in_n_II_UIM : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_neg_MC_D1_PT_0 : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_neg_MC_D1 : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_neg_MC_D2 : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_pos_MC_Q : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_pos_MC_D : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_pos_MC_D1_PT_0 : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_pos_MC_D1 : STD_LOGIC;   signal spi_intrface_spi_ctrl_sm_ss_in_pos_MC_D2 : STD_LOGIC;   signal uc_intrface_spierr_reset_MC_Q : STD_LOGIC;   signal uc_intrface_spierr_reset_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_spierr_reset_MC_D : STD_LOGIC;   signal uc_intrface_spierr_reset_MC_D1 : STD_LOGIC;   signal uc_intrface_spierr_reset_MC_D2_PT_0 : STD_LOGIC;   signal uc_intrface_spierr_reset_MC_D2_PT_1 : STD_LOGIC;   signal uc_intrface_stat_en : STD_LOGIC;   signal uc_intrface_spierr_reset_MC_D2_PT_2 : STD_LOGIC;   signal uc_intrface_spierr_reset_MC_D2_PT_3 : STD_LOGIC;   signal uc_intrface_spierr_reset_MC_D2 : STD_LOGIC;   signal uc_intrface_spierr_reset_MC_D_TFF : STD_LOGIC;   signal uc_intrface_stat_en_MC_Q : STD_LOGIC;   signal uc_intrface_stat_en_MC_R_OR_PRLD : STD_LOGIC;   signal uc_intrface_stat_en_MC_D : STD_LOGIC;   signal uc_intrface_stat_en_MC_D1_PT_0 : STD_LOGIC;   signal uc_intrface_stat_en_MC_D1 : STD_LOGIC;   signal uc_intrface_stat_en_MC_D2 : STD_LOGIC;   signal addr_data_0_MC_D1 : STD_LOGIC;   signal addr_data_0_MC_UIM : STD_LOGIC;   signal N_PZ_721 : STD_LOGIC;   signal addr_data_0_MC_D2_PT_0 : STD_LOGIC;   signal uc_intrface_ssel_en : STD_LOGIC;   signal addr_data_0_MC_D2_PT_1 : STD_LOGIC;   signal uc_intrface_rcv_en : STD_LOGIC;   signal addr_data_0_MC_D2_PT_2 : STD_LOGIC;   signal uc_intrface_xmit_en : STD_LOGIC;   signal addr_data_0_MC_D2_PT_3 : STD_LOGIC;   signal uc_intrface_rcv_cpol : STD_LOGIC;   signal addr_data_0_MC_D2_PT_4 : STD_LOGIC;   signal addr_data_0_MC_D2 : STD_LOGIC;