SRAM_SADDR    EQU 0x60000000        ; SRAM starting address
ISR_BADDR     EQU 0x60000000        ; plus 0x20 is the RW base address -linker setting
SFR_BADDR     EQU 0x80000000

SRAM_SIZE     EQU 48*1024           ; 48K internal SRAM
SRAM_EADDR    EQU SRAM_SADDR+SRAM_SIZE-1 ; SRAM end address

_SVC_STKSIZE  EQU 1024*20
_UND_STKSIZE  EQU 256
_ABT_STKSIZE  EQU 256
_IRQ_STKSIZE  EQU 1024*1
_FIQ_STKSIZE  EQU 256

STK_SIZE      EQU _SVC_STKSIZE+_UND_STKSIZE+_ABT_STKSIZE+_IRQ_STKSIZE+_FIQ_STKSIZE

STK_SADDR     EQU SRAM_EADDR+1-STK_SIZE

;Register definition
rMEMCFG1      EQU SFR_BADDR+0x0180
rMEMCFG2      EQU SFR_BADDR+0x01C0
rINTMR1       EQU SFR_BADDR+0x0280
rINTMR2       EQU SFR_BADDR+0x1280
rINTSR1       EQU SFR_BADDR+0x0240
rINTSR2       EQU SFR_BADDR+0x1240
rSDCONF       EQU SFR_BADDR+0x2300
rSDRFPR       EQU SFR_BADDR+0x2340
rSYSCON1      EQU SFR_BADDR+0x0100
rSYSCON2      EQU SFR_BADDR+0x1100
rSYSCON3      EQU SFR_BADDR+0x2200


rPADR        	EQU	SFR_BADDR+0x0000
rPBDR		EQU	SFR_BADDR+0x0001
rPADDR		EQU 	SFR_BADDR+0x0040
rPBDDR		EQU	SFR_BADDR+0x0041


;Pre-defined constants
USERMODE      EQU 0x10
FIQMODE       EQU 0x11
IRQMODE       EQU 0x12
SVCMODE       EQU 0x13
ABORTMODE     EQU 0x17
UNDEFMODE     EQU 0x1b
MODEMASK      EQU 0x1f
NOINT         EQU 0xc0


        MACRO
$HandlerLabel HANDLER $HandleLabel
						;;			
$HandlerLabel					;;			r0	<----sp
        sub sp,sp,#4				;;	<---sp		HandleLabel
        stmfd sp!,{r0}				;;  	<---origin sp			
        ldr r0,=$HandleLabel
        ldr r0,[r0]
        str r0,[sp,#4]
        ldmfd sp!,{r0,pc}
        MEND


        AREA  Init, CODE, READONLY;|Assembly$$code|, CODE, READONLY

        ENTRY

        b ResetHandler              ;for debug
        b HandlerUndef              ;handlerUndef
        b HandlerSWI                ;SWI interrupt handler
        b HandlerPabort             ;handlerPAbort
        b HandlerDabort             ;handlerDAbort
        b .                         ;handlerReserved		;loop here
        b HandlerIRQ                ;handlerIRQ
        b HandlerFIQ                ;handlerFIQ

HandlerFIQ     HANDLER HandleFIQ
HandlerIRQ     HANDLER HandleIRQ
HandlerUndef   HANDLER HandleUndef
HandlerSWI     HANDLER HandleSWI
HandlerDabort  HANDLER HandleDabort
HandlerPabort  HANDLER HandlePabort


;*****************************************************************************
;
; ResetHandler is the startup code to be used
;
;*****************************************************************************
ResetHandler
        ldr r0,=0x00000000
        ;        
        ;disable all interrupts (they should be disabled on reset, but just in case...)

        ldr r12,=rINTMR1
        str r0,[r12]                ;INTMR1 = 0x8000.0280
        ldr r12,=rINTMR2
        str r0,[r12]                ;INTMR2 = 0x8000.1280
         
        ;
        ; Set bits 1:2 in SYSCON3 for 74 MHz clock speed (default is 18MHz on reset)
        ;
        ldr r1,=0x06
        ldr r12,=rSYSCON3
        str r1,[r12]                ;init syscon3 register at 0x8000.2200
	
	;sdram config

; Now configure the MemConfig register to get the following:
;
; nCS0 = NOR FLASH, 32-bit, 3 wait states
; nCS1 = NAND FLASH, 32-bit, 2 wait states
; nCS2 = Ethernet, 16-bit, 8 wait states (was 32-bit =0x00)
; nCS3 = Parallel/Keyboard/GPIOs, 8-bit, 1 wait state
; nCS4 = USB, 8-bit, 1 wait state, 2 w/s random (was 32-bit, =0x3c)
; nCS5 = Unused/general purpose, 32-bit, 8 wait states
;
                
MemConfig1value  EQU 0x1201190c		;12
MemConfig2value  EQU 0x0000013d     ;boot rom and internal SRAM are ignored 
        
        ;
        ; configure nCS0-nCS3
        ;
        ldr r1,=MemConfig1value
        ldr r12,=rMEMCFG1
        str r1,[r12]                ;MEMCFG1 = 0x8000.0180
        ;
        ; configure nCS4 &nCS5
        ;
        ldr r1,=MemConfig2value
        ldr r12,=rMEMCFG2
        str r1,[r12]                ;MEMCFG2 = 0x8000.01c0
	
; **************************************************************************
; Define Stacks
; The follow section defines the stack pointer for IRQ and SVC modes.
; This is optional as the debugger will assign it's own stack area with the
; $top_of_memory variable in "debugger internals".
; However, this code is necessary if this program is used to launch an 
; embedded applications in C or assembly.
; **************************************************************************
        ldr sp,=SVCStack            ;

        bl InitStacks

	




        ;Call the actual C program.
        ;
        IMPORT c_entry

        bl c_entry                  ;C Entry
	



;
; Normally, the program should not return, but just in case, branch to the 
; reset vector and start over.

        b ResetHandler              ; Precautionary


InitStacks
        ;Don't use DRAM,such as stmfd,ldmfd......
        ;SVCstack is initialized before
        ;Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
        
        mrs r0,cpsr
        bic r0,r0,#MODEMASK
        orr r1,r0,#UNDEFMODE|NOINT
        msr cpsr,r1            ;UndefMode
        ldr sp,=UndefStack
        
        orr r1,r0,#ABORTMODE|NOINT
        msr cpsr,r1            ;AbortMode
        ldr sp,=AbortStack

        orr r1,r0,#IRQMODE|NOINT
        msr cpsr,r1            ;IRQMode
        ldr sp,=IRQStack
        
        orr r1,r0,#FIQMODE|NOINT
        msr cpsr,r1            ;FIQMode
        ldr sp,=FIQStack

        bic r0,r0,#MODEMASK|NOINT
        orr r1,r0,#SVCMODE
        msr cpsr,r1            ;SVCMode
        ldr sp,=SVCStack

        ;USER mode is not initialized.

        mov pc,lr                   ;The LR register may be not valid for the mode changes.

;
;*****************************************************************************
;
; Zero-initialized read/write data area for stacks.
; This area is determined by the RW value in the Linker under "entry and base".  
;*****************************************************************************
        AREA  SYS_STK, DATA, READWRITE, NOINIT

;*****************************************************************************
;
; Memory buffers to contain the stacks for the various processor modes which
; we will be using.
;
;*****************************************************************************

        ^       STK_SADDR

UserStack       #       _SVC_STKSIZE
SVCStack        #       _UND_STKSIZE
UndefStack      #       _ABT_STKSIZE
AbortStack      #       _IRQ_STKSIZE
IRQStack        #       _FIQ_STKSIZE
FIQStack        #       0 


        AREA  ISR_HOOK, DATA, READWRITE, NOINIT

        ^  ISR_BADDR		;;^,,set the address ISR_BADDR
HandleReset     # 4
HandleUndef     # 4
HandleSWI       # 4
HandlePabort    # 4
HandleDabort    # 4
HandleReserved  # 4
HandleIRQ       # 4
HandleFIQ       # 4

;
;*****************************************************************************
;        
        END