?? can_top.ldo
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# Auto generated by Project Navigator for Modelsim
vlib work
vlog can_register_asyn_syn.v
vlog can_register_asyn.v
vlog can_register.v
vlog can_registers.v
vlog can_btl.v
vlog can_crc.v
vlog can_acf.v
vlog can_fifo.v
vlog can_ibo.v
vlog can_bsp.v
vlog can_top.v
vlog "C:/Program Files/Xilinx/verilog/src/glbl.v"
## You need to generate your own stimuli
vsim -t 1ps +maxdelays -L xilinxcorelib_ver -L unisims_ver can_top glbl
view wave
add wave *
view structure
view signals
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