/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name          : stm32f10x_tim1.h
* Author             : MCD Application Team
* Date First Issued  : 09/29/2006
* Description        : This file contains all the functions prototypes for the 
*                      TIM1 firmware library.
********************************************************************************
* History:
* 02/05/2007: V0.1
* 09/29/2006: V0.01
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_TIM1_H
#define __STM32F10x_TIM1_H

/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"

/* Exported types ------------------------------------------------------------*/

/* TIM1 Time Base Init structure definition */
typedef struct
{
  u16 TIM1_Prescaler;
  u16 TIM1_CounterMode;
  u16 TIM1_Period;
  u16 TIM1_ClockDivision;
  u8 TIM1_RepetitionCounter;
} TIM1_TimeBaseInitTypeDef;

/* TIM1 Output Compare Init structure definition */
typedef struct
{
  u8 TIM1_OCMode;
  u16 TIM1_OutputState;
  u16 TIM1_OutputNState;
  u16 TIM1_Pulse;
  u8 TIM1_OCPolarity;
  u8 TIM1_OCNPolarity;
  u16 TIM1_OCIdleState;
  u16 TIM1_OCNIdleState;
} TIM1_OCInitTypeDef;

/* TIM1 Input Capture Init structure definition */
typedef struct
{
  u8 TIM1_Channel;
  u8 TIM1_ICPolarity;
  u8 TIM1_ICSelection;
  u8 TIM1_ICPrescaler;
  u8 TIM1_ICFilter;
} TIM1_ICInitTypeDef;

/* BDTR structure definition */
typedef struct
{
  u16 TIM1_OSSRState;
  u16 TIM1_OSSIState;
  u16 TIM1_LOCKLevel; 
  u16 TIM1_DeadTime;
  u16 TIM1_Break;
  u16 TIM1_BreakPolarity;
  u16 TIM1_AutomaticOutput;
} TIM1_BDTRInitTypeDef;

/* Exported constants --------------------------------------------------------*/
/* TIM1 Output Compare and PWM modes */
#define TIM1_OCMode_Timing                 ((u16)0x0000)
#define TIM1_OCMode_Active                 ((u16)0x0010)
#define TIM1_OCMode_Inactive               ((u16)0x0020)
#define TIM1_OCMode_Toggle                 ((u16)0x0030)
#define TIM1_OCMode_PWM1                   ((u16)0x0060)
#define TIM1_OCMode_PWM2                   ((u16)0x0070)

/* TIM1 One Pulse Mode */
#define TIM1_OPMode_Single                 ((u16)0x0001)
#define TIM1_OPMode_Repetitive             ((u16)0x0000)

/* TIM1 Channel */
#define TIM1_Channel_1                     ((u16)0x0000)
#define TIM1_Channel_2                     ((u16)0x0001)
#define TIM1_Channel_3                     ((u16)0x0002)
#define TIM1_Channel_4                     ((u16)0x0003)

/* TIM1 Clock Division CKD */
#define TIM1_CKD_DIV1                      ((u16)0x0000)
#define TIM1_CKD_DIV2                      ((u16)0x0100)
#define TIM1_CKD_DIV4                      ((u16)0x0200)

/* TIM1 Counter Mode */
#define TIM1_CounterMode_Up                ((u16)0x0000)
#define TIM1_CounterMode_Down              ((u16)0x0010)
#define TIM1_CounterMode_CenterAligned1    ((u16)0x0020)
#define TIM1_CounterMode_CenterAligned2    ((u16)0x0040)
#define TIM1_CounterMode_CenterAligned3    ((u16)0x0060)

/* TIM1 Output Compare Polarity */
#define TIM1_OCPolarity_High               ((u16)0x0000)
#define TIM1_OCPolarity_Low                ((u16)0x0001)

/* TIM1 Output Compare N Polarity */
#define TIM1_OCNPolarity_High              ((u16)0x0000)
#define TIM1_OCNPolarity_Low               ((u16)0x0001)

/* TIM1 Output Compare states */
#define TIM1_OutputState_Disable           ((u16)0x0000)
#define TIM1_OutputState_Enable            ((u16)0x0001)

/* TIM1 Output Compare N States */
#define TIM1_OutputNState_Disable          ((u16)0x0000)
#define TIM1_OutputNState_Enable           ((u16)0x0001)

/* Break Input enable/disable */
#define TIM1_Break_Enable                  ((u16)0x1000)
#define TIM1_Break_Disable                 ((u16)0x0000)

/* Break Polarity */
#define TIM1_BreakPolarity_Low             ((u16)0x0000)
#define TIM1_BreakPolarity_High            ((u16)0x2000)

/* TIM1 AOE Bit Set/Reset */
#define TIM1_AutomaticOutput_Enable        ((u16)0x4000)
#define TIM1_AutomaticOutput_Disable       ((u16)0x0000)

/* Lock levels */
#define TIM1_LOCKLevel_OFF                 ((u16)0x0000)
#define TIM1_LOCKLevel_1                   ((u16)0x0100)
#define TIM1_LOCKLevel_2                   ((u16)0x0200)
#define TIM1_LOCKLevel_3                   ((u16)0x0300)

/* OSSI: Off-State Selection for Idle mode states */
#define TIM1_OSSIState_Enable              ((u16)0x0400)
#define TIM1_OSSIState_Disable             ((u16)0x0000)

/* OSSR: Off-State Selection for Run mode states */
#define TIM1_OSSRState_Enable              ((u16)0x0800)
#define TIM1_OSSRState_Disable             ((u16)0x0000)

/* TIM1 Output Compare Idle State */
#define TIM1_OCIdleState_Set               ((u16)0x0001)
#define TIM1_OCIdleState_Reset             ((u16)0x0000)

/* TIM1 Output Compare N Idle State */
#define TIM1_OCNIdleState_Set              ((u16)0x0001)
#define TIM1_OCNIdleState_Reset            ((u16)0x0000)

/* TIM1 Input Capture Polarity */
#define  TIM1_ICPolarity_Rising            ((u16)0x0000)
#define  TIM1_ICPolarity_Falling           ((u16)0x0001)

/* TIM1 Input Capture Selection */
#define TIM1_ICSelection_DirectTI          ((u16)0x0001)
#define TIM1_ICSelection_IndirectTI        ((u16)0x0002)
#define TIM1_ICSelection_TRGI              ((u16)0x0003)

/* TIM1 Input Capture Prescaler */
#define TIM1_ICPSC_DIV1                    ((u16)0x0000)
#define TIM1_ICPSC_DIV2                    ((u16)0x0004)
#define TIM1_ICPSC_DIV4                    ((u16)0x0008)
#define TIM1_ICPSC_DIV8                    ((u16)0x000C)

/* TIM1 interrupt sources */
#define TIM1_IT_Update                     ((u16)0x0001)
#define TIM1_IT_CC1                        ((u16)0x0002)
#define TIM1_IT_CC2                        ((u16)0x0004)
#define TIM1_IT_CC3                        ((u16)0x0008)
#define TIM1_IT_CC4                        ((u16)0x0010)
#define TIM1_IT_COM                        ((u16)0x0020)
#define TIM1_IT_Trigger                    ((u16)0x0040)
#define TIM1_IT_Break                      ((u16)0x0080)

/* TIM1 DMA Base address */
#define TIM1_DMABase_CR1                   ((u16)0x0000)
#define TIM1_DMABase_CR2                   ((u16)0x0001)
#define TIM1_DMABase_SMCR                  ((u16)0x0002)
#define TIM1_DMABase_DIER                  ((u16)0x0003)
#define TIM1_DMABase_SR                    ((u16)0x0004)
#define TIM1_DMABase_EGR                   ((u16)0x0005)
#define TIM1_DMABase_CCMR1                 ((u16)0x0006)
#define TIM1_DMABase_CCMR2                 ((u16)0x0007)
#define TIM1_DMABase_CCER                  ((u16)0x0008)
#define TIM1_DMABase_CNT                   ((u16)0x0009)
#define TIM1_DMABase_PSC                   ((u16)0x000A)
#define TIM1_DMABase_ARR                   ((u16)0x000B)
#define TIM1_DMABase_RCR                   ((u16)0x000C)
#define TIM1_DMABase_CCR1                  ((u16)0x000D)
#define TIM1_DMABase_CCR2                  ((u16)0x000E)
#define TIM1_DMABase_CCR3                  ((u16)0x000F)
#define TIM1_DMABase_CCR4                  ((u16)0x0010)
#define TIM1_DMABase_BDTR                  ((u16)0x0011)
#define TIM1_DMABase_DCR                   ((u16)0x0012)

/* TIM1 DMA Burst Length */
#define TIM1_DMABurstLength_1Byte          ((u16)0x0000)
#define TIM1_DMABurstLength_2Bytes         ((u16)0x0100)
#define TIM1_DMABurstLength_3Bytes         ((u16)0x0200)