JDF B
// Created by Version 8.0 
PROJECT nand_flash_cntl
DESIGN nand_flash_cntl Normal
DEVKIT LCMXO2280C-5T100C
ENTRY Mixed Verilog/VHDL
TESTFIXTURE ..\..\..\testbench\verilog\nfcm_tb.v
TESTDEPFILE ../../../testbench/verilog/nfcm_tb.v ../../../testbench/verilog/flash_interface.v
MODULE ..\..\..\source\verilog\ErrLoc.v
MODSTYLE ErrLoc Normal
MODULE ..\..\..\source\verilog\H_gen.v
MODSTYLE H_gen Normal
MODULE ..\..\..\source\verilog\MFSM.v
MODSTYLE MFSM Normal
MODULE ..\..\..\source\verilog\TFSM.v
MODSTYLE TFSM Normal
MODULE ..\..\..\source\verilog\ACounter.v
MODSTYLE ACounter Normal
MODULE ..\..\..\source\verilog\ipexpress\xo\ebr_buffer.v
MODSTYLE ebr_buffer Normal
MODULE ..\..\..\source\verilog\nfcm_top.v
MODSTYLE nfcm_top Normal
SYNTHESIS_TOOL Synplify
SIMULATOR_TOOL ActiveHDL
AUTO_READ_DESIGN TRUE
TOPMODULE nfcm_top