//-------------------------------------------------------------------------
//  >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
//-------------------------------------------------------------------------
//  Copyright (c) 2006-2010 by Lattice Semiconductor Corporation      
// 
//-------------------------------------------------------------------------
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//-------------------------------------------------------------------------
//
//    Lattice Semiconductor Corporation
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//-------------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author :| Mod. Date :| Changes Made:
//   V01.0:| A.Y    :| 09/30/06  :| Initial ver
//   v01.1:| J.T    :| 06/21/09  :| just use one buffer
// --------------------------------------------------------------------
//
// 
//Description of module:
//--------------------------------------------------------------------------------
//This module interprets commands from the Host, passes control to TFSM to execute 
//repeating regular tasks with strict timing requirements.
// --------------------------------------------------------------------
`timescale 1 ns / 1 fs
module MFSM(
  CLK,
  RES,
  start,
  command,
  setDone,
  R_nB,
  BF_sel,
//  TBF,
//  RBF,//  -- tx & rx buffer rd flags
//  ResTBF,
//  SetRBF,
  mBF_sel,
  BF_we,
  io_0,
  t_start,
  t_cmd,
  t_done,
  WrECC,
  EnEcc,
//  ecc2flash,
//  byteSelCntEn,
//  byteSelCntRes,
  AMX_sel,
  cmd_reg,
  cmd_reg_we,
  RAR_we,
//  ADS,
  set835,
  cnt_res,
  tc8,
  tc4,// -- term counts fm Wait counter
  wCntRes,
  wCntCE,//  -- wait conter ctrl
  SetPrErr,
  SetErErr,
//  SetBFerr,
  ADC_sel// -- ad/dat/cmd mux ctrl
)/*synthesis ugroup="mfsm_group" */;  
 input CLK;
 input RES;    
 input start;
 input [2:0] command;  
 input R_nB;         
 input BF_sel;       
// input TBF;          
// input RBF;//  -- tx 
 input io_0; 
 input t_done; 
 input tc8;          
 input tc4;// -- term
   
 output reg setDone;
// output reg ResTBF;       
// output reg SetRBF;
 output mBF_sel;
 output reg BF_we;       
 output reg t_start;      
 output reg [2:0] t_cmd;
 output reg WrECC;
 output reg EnEcc;
// output reg ecc2flash; 
// output reg byteSelCntEn;
// output reg byteSelCntRes;
 output reg [1:0] AMX_sel;      
 output reg [7:0] cmd_reg;      
 output reg cmd_reg_we; 
 output reg RAR_we;
// output reg ADS;       
 output reg set835;       
 output reg cnt_res;      
 output reg wCntRes;      
 output reg wCntCE;//  -- 
 output reg SetPrErr;     
 output reg SetErErr;     
// output reg SetBFerr;
 output reg [1:0] ADC_sel;// -- a
 
 parameter Init=0,S_ADS=1, S_RAR=2, 
S_CmdL0=3,S_CmdL1=4,S_adL0=5,S_adL1=6, S_CmdL2=7, S_CmdL3=8,//-- EBL
S_WC0=9, S_WC1=10, S_wait=11, S_CmdL4=12, S_CmdL5=13, S_WC3=14, S_WC4=15, S_DR1=16, S_Done=17,
Sr_RAR=18, Sr_DnErr=19, Sr_CmdL0=20, Sr_CmdL1=21, Sr_AdL0=22, Sr_AdL1=23, Sr_AdL2=24,// -- RPA
Sr_AdL3=25, Sr_CmdL2=26, Sr_CmdL3=27, Sr_WC0=28, Sr_WC1=29, Sr_wait=30, Sr_RPA0=31,
Sr_CmdL4=32, Sr_CmdL5=33, Sr_AdL4=34, Sr_AdL5=35, Sr_CmdL6=36, Sr_CmdL7=37, Sr_WC2=38,Sr_RPA1=39,
Sr_wait1=40, Sr_wait2=41, Sr_WC3=42, Sr_Done=43,
Sw_RAR=44, Sw_CmdL0=45, Sw_CmdL1=46, Sw_AdL0=47, Sw_AdL1=48, Sw_AdL2=49, Sw_AdL3=50,Sw_WPA0=51,// -- WPA
Sw_CmdL2=52, Sw_CmdL3=53,  Sw_AdL4=54, Sw_AdL5=55, Sw_WPA1=56, 
Swait3=57, Sw_CmdL4=58, Sw_CmdL5=59, Sw_WC1=60, Sw_WC2=61, Sw_CmdL6=62,
Sw_CmdL7=63, Sw_DR1=64, Sw_Wait4=65, Sw_Wait5=66, Sw_done=67,
Srst_RAR=68, Srst_CmdL0=69, Srst_CmdL1=70,Srst_done=71,
Srid_RAR=72, Srid_CmdL0=73, Srid_CmdL1=74, Srid_AdL0=75,
Srid_Wait=76, Srid_DR1=78, Srid_DR2=79, Srid_DR3=80, Srid_DR4=81, Srid_done=82;


reg [7:0] NxST,CrST;
reg BF_sel_int;

parameter C0=4'b0000,          C1=4'b0001,          C3=4'b0011,          C5=4'b0101,          C6=4'b0110,          C7=4'b0111,          C8=4'b1000,          CD=4'b1101,          CE=4'b1110,
          CF=4'b1111,
          C9=4'b1001;
          
assign mBF_sel=BF_sel_int;// buff clock enable

always@(posedge CLK)
 if(start)
  BF_sel_int<=BF_sel;  
  
always@(posedge CLK)
 CrST<=NxST;
 
//always@(RES or command or start or R_nB or TBF or RBF or t_done or tc4 or tc8 or io_0 or CrST)
always@(RES or command or start or R_nB or t_done or tc4 or tc8 or io_0 or CrST)
 if(RES) begin
  NxST <= Init;
  setDone <= 0;
//  ResTBF <= 1;
//  SetRBF <= 0;
  BF_we <= 0;
  t_start <= 0;
  t_cmd <= 3'b011; // nop
  WrECC <= 0;
  EnEcc <= 0;
//  ecc2flash <= 0;
//  byteSelCntEn <= 0;
//  byteSelCntRes <= 1;  
  AMX_sel <= 2'b00;
  cmd_reg <= 8'b00000000;
  cmd_reg_we <= 0;
//  ADS <= 0;
  set835 <= 0;
  cnt_res <= 0;
  wCntRes <= 0;
  wCntCE <= 0;
  ADC_sel <=2'b11;  // cmd to out
  SetPrErr <= 0;
  SetErErr <= 0;
//  SetBFerr <= 0;
  RAR_we <= 0;
  
end else begin           // default values
    setDone <= 0;
//    ResTBF <= 0;
//    SetRBF <= 0;
    BF_we <= 0;
    t_start <=0;
    t_cmd <= 3'b011; // nop
    WrECC <= 0;
    EnEcc <= 0;
//    ecc2flash <= 0;
//    byteSelCntEn <= 0;
//    byteSelCntRes <= 0;  
    AMX_sel <= 2'b00;
    cmd_reg <= 8'b00000000;
    cmd_reg_we <= 0;
//    ADS <= 0;
    set835 <= 0;
    cnt_res <= 0;
    wCntRes <= 0;
    wCntCE <= 0;
    ADC_sel <= 2'b11;
    SetPrErr <= 0;
    SetErErr <= 0;
//    SetBFerr <= 0;
    RAR_we <= 0; 

  case(CrST)
    Init:begin
      if (start)
        NxST <=S_ADS;
      else
        NxST <=Init;
    end
    S_ADS:begin
//      ADS <= 1;
      cnt_res <= 1;
      if (command ==3'b100) //EBL
        NxST <= S_RAR;
      else if (command==3'b010) //RPA
        NxST <= Sr_RAR;
      else if (command==3'b001) //WPA
        NxST <= Sw_RAR;
      else if (command==3'b011)
        NxST <= Srst_RAR; 
      else if (command==3'b101)
        NxST <= Srid_RAR;   
      else begin
        setDone <= 1;       // nop
        NxST <= Init;
        SetPrErr <=1;
        SetErErr <= 1;
      end
    end
    S_RAR:begin //          --EBL
      RAR_we <= 1;//--strobe the row address from the host
      NxST <= S_CmdL0;
    end
    S_CmdL0:begin
      cmd_reg <= {C6,C0};
      cmd_reg_we <= 1;
      NxST <= S_CmdL1;
    end
    S_CmdL1:begin
      t_start <= 1;
      t_cmd <= 3'b000; //-- cmd_latch
      if (t_done == 1)
        NxST <= S_adL0;
      else
        NxST <= S_CmdL1;
    end
    S_adL0:begin
      t_start <= 1;
      t_cmd <= 3'b001;// -- ad_latch
      ADC_sel <= 2'b10;// -- addr to out
      AMX_sel <= 2'b10;// -- ra1
      if (t_done == 1)
        NxST <= S_adL1;
      else
        NxST <= S_adL0;
    end
    S_adL1:begin
      t_start <=1;
      t_cmd <= 3'b001;// -- ad_latch
      ADC_sel <=2'b10;// -- addr to out      
      AMX_sel <=2'b11;// -- ra2
      if (t_done ==1)
        NxST <= S_CmdL2;
      else
        NxST <= S_adL1;
    end 
    S_CmdL2:begin
      cmd_reg <= {CD,C0};
      cmd_reg_we <= 1;
      NxST <= S_CmdL3;
    end
    S_CmdL3:begin
      t_start <= 1;
      t_cmd <=3'b000;// -- cmd_latch
      if (t_done ==1) 
        NxST <= S_WC0;
      else
        NxST <= S_CmdL3;
    end
    S_WC0:begin
      wCntRes <=1;
      NxST <= S_WC1;
    end
    S_WC1:begin
      wCntCE <=1;
      if (tc8 == 1)
        NxST <= S_wait;
      else
        NxST <= S_WC1;
    end
    S_wait:begin
      if (R_nB ==1)
        NxST <= S_CmdL4;
      else
        NxST <= S_wait;
    end 
    S_CmdL4:begin
      cmd_reg <= {C7,C0};
      cmd_reg_we <= 1;
      NxST <= S_CmdL5;
    end
    S_CmdL5:begin
      t_start <= 1;
      t_cmd <= 3'b000;// -- cmd_latch
      if (t_done ==1)
        NxST <= S_WC3;
      else
        NxST <= S_CmdL5;
    end
    S_WC3:begin
      wCntRes <= 1;
      NxST <= S_WC4;
    end
    S_WC4:begin
      wCntCE <=1;
      if (tc4 ==1)
        NxST <= S_DR1;
      else
        NxST <= S_WC4;
    end 
    S_DR1:begin
      t_start <= 1;
      t_cmd <= 3'b010;// -- data read 1 (status)
      if (t_done ==1)
        NxST <= S_Done;
      else
        NxST <= S_DR1;      
    end 
    S_Done:begin
      setDone <=1;
      NxST <= Init;
      if (io_0 == 1)
        SetErErr <= 1;
      else
        SetErErr <= 0;
    end    
    Sr_RAR:begin
      RAR_we <= 1;
  //    if (RBF==0)
        NxST <= Sr_CmdL0;
  //    else begin
  //      NxST <= Init;
  //      SetBFerr <=1;
  //      setDone <=1;
  //    end 
    end
    Sr_CmdL0:begin
      cmd_reg <= {C0,C0};
      cmd_reg_we <= 1;
      NxST <= Sr_CmdL1;
    end
    Sr_CmdL1:begin
      t_start <= 1;
      t_cmd <= 3'b000;// -- cmd_latch
      if (t_done ==1)
        NxST <= Sr_AdL0;
      else
        NxST <= Sr_CmdL1;
    end 
    Sr_AdL0:begin
      t_start <= 1;
      t_cmd <= 3'b001;// -- ad_latch
      ADC_sel <= 2'b10; //-- addr to out      
      AMX_sel <= 2'b00;// -- ca1
      if (t_done ==1)
        NxST <= Sr_AdL1;
      else
        NxST <= Sr_AdL0;
    end 
    Sr_AdL1:begin
      t_start <= 1;
      t_cmd <= 3'b001;// -- ad_latch
      ADC_sel <= 2'b10; //-- addr to out      
      AMX_sel <= 2'b01;// -- ca2
      if (t_done==1)
        NxST <= Sr_AdL2;
      else
        NxST <= Sr_AdL1;
    end
    Sr_AdL2:begin
      t_start <= 1;
      t_cmd <= 3'b001;// -- ad_latch
      ADC_sel <= 2'b10; //-- addr to out      
      AMX_sel <= 2'b10;// -- ra1
      if (t_done ==1)
        NxST <= Sr_AdL3;
      else
        NxST <= Sr_AdL2;
    end 
    Sr_AdL3:begin
      t_start <= 1;
      t_cmd <= 3'b001;// -- ad_latch
      ADC_sel <= 2'b10;// -- addr to out      
      AMX_sel <= 2'b11;// -- ra2
      if (t_done ==1)
        NxST <= Sr_CmdL2;
      else
        NxST <= Sr_AdL3;
    end
    Sr_CmdL2:begin
      cmd_reg <= {C3,C0};