/* Testfixture for Manchester decoder   Xilinx, Inc   Jan 26, 2000 */'timescale 1 ns / 1 nsmodule md_tf ;reg rst ;reg clk16x ;reg mdi ;reg clk1x_enable ;reg clk1x ;reg nrz ;reg [3:0] no_bits_rcvd ;reg sample ;reg rdn ;wire [7:0] dout ;md u1 (rst,clk16x,mdi,rdn,dout,data_ready) ;initial beginrst = 1'b0 ;clk16x = 1'b0 ;mdi = 1'b0 ;rdn = 1'b1 ;endinteger md_chann ;initial beginmd_chann=$fopen("md.rpt") ;$timeformat(-9,,,5) ;endparameter clock_period = 100 ;always #(clock_period/2) clk16x = ~clk16x ;initial begin$fdisplay(md_chann,"Verilog simulation of Manchester decoder\n\n") ;$shm_open("md.shm") ;$shm_probe("AS") ;$fmonitor(md_chann,"Time=%t,rst=%b,clk16=%b,clk1x=%b,mdi=%b,nrz=%b,no_bits_rcvd=%b,sample=%b,dout=%h,data_ready=%b",$time,rst,clk16x,md.clk1x_enable,md.clk1x,mdi,md.nrz,md.no_bits_rcvd,md.sample,dout,data_ready) ;#1 rst = 1'b1 ;#100 rst = 1'b0 ;// Input 8 logic 0s#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#1600 rdn = 1'b0 ;#800 rdn = 1'b1 ;#3200// Input 8 logic 1s  #800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#800 mdi = 1'b1 ;#800 mdi = 1'b0 ;#2400 rdn = 1'b0 ;#800 rdn = 1'b1 ;// Input alternating 1s, 0s#1600 mdi = 1'b1 ;#1600 mdi = 1'b0 ;#1600 mdi = 1'b1 ;#1600 mdi = 1'b0 ;#1600 mdi = 1'b1 ;#1600 mdi = 1'b0 ;#1600 mdi = 1'b1 ;#1600 mdi = 1'b0 ;#1600 rst = 1'b1 ;$fdisplay (md_chann,"\nSimulation of Manchester decoder is complete.") ;$finish ;endendmodule