---實現的部分VHDL 程序如下。
--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----數據幀數據由接收串行數據端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器數據進入接收緩沖器--- ...... --- end if
標簽:
clk1x
std_logic_vector
length_no
elsif
上傳時間:
2015-10-28
上傳用戶:cainaifa