This Verilog HDL description implements a UART.
標(biāo)簽： description implements Verilog This
上傳時(shí)間： 2013-12-17
上傳用戶：wff
this a Uart source code using Verilog.
標(biāo)簽： Verilog source using this
上傳時(shí)間： 2016-05-19
上傳用戶：zsjzc
This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments
標(biāo)簽： description implements Creation Original
上傳時(shí)間： 2016-05-27
上傳用戶：1109003457
This is a uart source written by VHDL .widely used and compatible with Whibone.
標(biāo)簽： compatible Whibone written source
上傳時(shí)間： 2013-12-22
上傳用戶：cxl274287265
intercept tty is using for listening a UART conversation
標(biāo)簽： conversation intercept listening using
上傳時(shí)間： 2017-04-12
上傳用戶：wangdean1101
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標(biāo)簽： PicoBlaze Create Master Xilinx
上傳時(shí)間： 2013-11-05
上傳用戶：a6697238
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標(biāo)簽： PicoBlaze Create Master Xilinx
上傳時(shí)間： 2013-11-12
上傳用戶：大三三
SDRAM 參考設(shè)計(jì):主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM
標(biāo)簽： high-level following reference diagram
上傳時(shí)間： 2013-12-15
上傳用戶：Miyuki
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標(biāo)簽： M5310 物聯(lián)網(wǎng) 4G模塊
上傳時(shí)間： 2022-06-24
上傳用戶：
Implementing a Software UART on the TMS320C54x with the McBSP and DMA
標(biāo)簽： Implementing the Software McBSP
上傳時(shí)間： 2014-11-30
上傳用戶：tuilp1a
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