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Abstract-In

基于C8051F930的管道溫度壓力遠程監測系統

為解決輸油管道溫度壓力參數實時監測的問題，設計了以C8051F930單片機作為控制核心的超低功耗輸油管道溫度壓力遠程監測系統。現場儀表使用高精度電橋采集數據，通過433 MHz短距離無線通信網絡與遠程終端RTU進行通信，RTU通過GPRS網絡與PC上位機進行遠程數據傳輸，在上位機中實現數據存儲和圖形化界面顯示，從而實現輸油管道溫度壓力參數的實時監測和異常報警。經實驗證明，該系統的12位數據采集精度滿足設計要求，漏碼率小于1%，正常工作時間超過5個月，能實時有效地監測輸油管道的溫度壓力參數，節省大量人工成本，有效預防管道參數異常造成的經濟損失和環境污染。 Abstract: In order to solve the problems on real-time monitoring of pipeline temperature and pressure parameters， the ultra-low power remote pipeline temperature and pressure monitoring system was designed by using the single chip processor C8051F930 as the control core. The high-precision electric bridge was used in field instruments for data collection， the 433MHz short-range wireless communication network was used to make communication between field instrument and RTU， the GPRS was used by the RTU to transmit data to the PC host computer， and the data was stored and displayed in the PC host computer， so the real-time monitoring and exception alerts of pipeline temperature and pressure parameters were achieved. The experiment proves that the system of which error rate is less than 1% over five months working with the 12-bit data acquisition accuracy can effectively monitor the pipeline temperature and pressure parameters in real time， it saves a lot of labor costs and effectively prevents environmental pollution and economic losses caused by abnormal channel parameters.

標簽： C8051F930 溫度壓力遠程監測系統

上傳時間： 2013-11-07

上傳用戶：cuibaigao
基于MSP430單片機和DS18B20的數字溫度計

為了在工業生產及過程控制中準確測量溫度，設計了一種基于低功耗MSP430單片機的數字溫度計。整個系統通過單片機MSP430F1121A控制DS18B20讀取溫度，采用數碼管顯示，溫度傳感器DS18B20與單片機之間通過串口進行數據傳輸。MSP430系列單片機具有超低功耗，且外圍的整合性高，DS18B20只需一個端口即可實現數據通信，連接方便。通過多次實驗證明，該系統的測試結果與實際環境溫度一致，除了具有接口電路簡單、測量精度高、誤差小、可靠性高等特點外，其低成本、低功耗的特點使其擁有更廣闊的應用前景。 Abstract: In order to obtain accurate measuring temperature in industrial production and process control， a digital thermometer based on MSP430 MCU is designed. The system uses MSP430F1121A MCU to control DS18B20， and gets the temperature data， which is displayed on the LED. The temperature sensor DS18B20 and MCU transmit data through serial communication. MSP430 series has ultra-low power and high integration， DS18B20 only needs one port to achieve data communication. Through many experimental results prove， this system is consistent with actual environment temperature. The system has characteristics of interface circuit simple， high measuring accuracy， minor error， high reliability， besides， the characteristics of low cost and low power make it having vaster application prospect.

標簽： MSP 430 18B B20

上傳時間： 2013-10-16

上傳用戶：wettetw
基于CPLD的QDPSK調制解調電路設計

為了在CDMA系統中更好地應用QDPSK數字調制方式，在分析四相相對移相（QDPSK)信號調制解調原理的基礎上，設計了一種QDPSK調制解調電路，它包括串并轉換、差分編碼、四相載波產生和選相、相干解調、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中，測試結果表明，調制電路能正確選相，解調電路輸出數據與QDPSK調制輸入數據完全一致，達到了預期的設計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.

標簽： QDPSK CPLD 調制解調電路設計

上傳時間： 2014-01-13

上傳用戶：qoovoop
基于碼本映射的語音帶寬擴展算法研究

在現代通信系統中，電話語音的頻帶被限制在300 Hz～4 kHz的范圍內，帶來了語音可懂度和自然度的降低。為了在不增加額外成本的前提下提高語音的可懂度和自然度，進行了電話語音頻帶擴展的研究。提出了一種改進的基于碼本映射的語音帶寬擴展算法：在碼本映射的過程中，使用加權系數來得到映射碼本。客觀測試結果表明，用此算法得到的寬帶語音的譜失真度比用一般的碼本映射降低至少2%。主觀測試結果表明，用此算法得到的寬帶語音具有更好的可懂度和自然度。 Abstract: In modern communication systems， the bandwidth of telephone speech is limited from 300Hz to 4 kHz， which reduces the intelligibility and naturalness of speech. Telephone speech bandwidth extension is researched to get wideband speech and to improve its intelligibility and naturalness， without increasing extra costs. This paper put forward an improved algorithm of speech bandwidth extension based on codebook mapping. In the process of codebook mapping， weighted coefficients were used to get mapping codebook. Objective tests show that spectral distortion of wideband speech obtained by this algorithm reduces at least 2%， comparing to conditional codebook mapping. Subjective tests show that the wideband speech obtained by this algorithm has better intelligibility and naturalness.

標簽： 映射帶寬擴展語音

上傳時間： 2014-12-29

上傳用戶：15501536189
開關磁阻電機驅動系統發展概況(講座)

本文介紹了開關磁阻電機驅動系統(Switched Reluctance Drive, SRD)的發展概況、系統構成以及目前的研究熱點。關鍵詞: 開關磁阻電機研究熱點 Abstract:In this paper, development, construction and research focus of Switched Reluctance Drive were introduced. Keywords: Switched Reluctance Motor Research focus 1 發展簡介開關磁阻電機(Switched Reluctance Motor, SRM)最早可以追溯到1970年，英國Leeds大學步進電機研究小組首創一個開關磁阻電機雛形。到1972年進一步對帶半導體開關的小功率電動機(10w～1kw)進行了研究。1975年有了實質性的進展，并一直發展到可以為50kw的電瓶汽車提供裝置。1980年在英國成立了開關磁阻電機驅動裝置有限公司(SRD Ltd.)，專門進行SRD系統的研究、開發和設計。1983年英國(SRD Ltd.)首先推出了SRD系列產品，該產品命名為OULTON。1984年TASC驅動系統公司也推出了他們的產品。另外SRD Ltd. 研制了一種適用于有軌電車的驅動系統，到1986年已運行500km。該產品的出現，在電氣傳動界引起不小的反響。在很多性能指標上達到了出人意料的高水平，整個系統的綜合性能價格指標達到或超過了工業中長期廣泛應用的一些變速傳動系統。下表是當時對幾種常用變速傳動系統各項主要經濟指標所作的比較。成本 1.0 1.5 1.0 美國、加拿大、南斯拉夫、埃及等國家也都開展了SRD系統的研制工作。在國外的應用中，SRD一般用于牽引中，例如電瓶車和電動汽車。同時高速性能是SRD的一個特長的方向。據報道，美國為空間技術研制了一個25000r/min、90kW的高速SRD樣機。我國大約在1985年才開始對SRD系統進行研究。SRD系統的研究已被列入我國中、小型電機“八五”、“九五”和“十五”科研規劃項目。華中科技大學開關磁阻電機課題組在“九五”項目中研制出使用SRD的純電動轎車，在“十五”項目中將SRD應用到混合動力城市公交車，均取得了較好的運行效果。紡織機械研究所將SRD應用于毛巾印花機、卷布機，煤礦牽引及電動車輛等，取得了顯著的經濟效益。從上世紀90年代國際會議的上有關SRD系統的文章來看，對SRD系統的研究工作已經從論證它的優點、開發應用階段進入到設計理論、優化設計研究階段。對SR電機、控制器、功率變換器等的運行理論、優化設計、結構形式等方面進行了更加深入的研究。

標簽： 開關磁阻電機發展驅動系統講座

上傳時間： 2013-10-11

上傳用戶：xjz632
智能天線技術在基站中的應用

為了能夠滿足基站易于選址、優質快速的建站要求和易維護、低成本、高可靠的運行要求，本文對以方艙來實現一體化結構基站做出一番探討。從系統設計的觀點闡述了移動通信高性能基站天線設計的幾個關鍵問題，介紹了智能天線技術在基站中的應用，并且用HFSS軟件仿真了一種新型的對稱陣子天線，該天線駐波比小于2的帶寬可以達到60%，具有良好的寬頻帶特性。 Abstract: In order to meet the station construction requirement of easy site selection and fast base station， and meet the operational requirement of easy maintenance， low cost and high reliability， this paper discussed the unified architecture base station using shelter. Several key problems of high performance mobile communication base station antenna were illustrated from the view of system design， the application of smart antenna in base station was also introduced. And a novel dipole antenna was simulated by using HFSS， the VSWR of the antenna is less than 2， and the bandwidth was reach to 60%. So it has good broadband properties.

標簽： 智能天線基站中的應用

上傳時間： 2013-11-20

上傳用戶：linlin
基于CPLD的QDPSK調制解調電路設計

為了在CDMA系統中更好地應用QDPSK數字調制方式，在分析四相相對移相（QDPSK)信號調制解調原理的基礎上，設計了一種QDPSK調制解調電路，它包括串并轉換、差分編碼、四相載波產生和選相、相干解調、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中，測試結果表明，調制電路能正確選相，解調電路輸出數據與QDPSK調制輸入數據完全一致，達到了預期的設計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.

標簽： QDPSK CPLD 調制解調電路設計

上傳時間： 2013-10-28

上傳用戶：jyycc
基于Verilog HDL設計的多功能數字鐘

本文利用Verilog HDL 語言自頂向下的設計方法設計多功能數字鐘，突出了其作為硬件描述語言的良好的可讀性、可移植性和易理解等優點，并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后，可應用于實際的數字鐘顯示中。關鍵詞：Verilog HDL；硬件描述語言；FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA

標簽： Verilog HDL 多功能數字

上傳時間： 2013-11-10

上傳用戶：hz07104032
基于EKF的異步電機直接轉矩控制系統

為了提高直接轉矩控制（DTC）系統定子磁鏈估計精度，降低電流、電壓測量的隨機誤差，提出了一種基于擴展卡爾曼濾波（EKF）實現異步電機轉子位置和速度估計的方法。擴展卡爾曼濾波器是建立在基于旋轉坐標系下由定子電流、電壓、轉子轉速和其它電機參量所構成的電機模型上，將定子電流、定子磁鏈、轉速和轉子角位置作為狀態變量，定子電壓為輸入變量，定子電流為輸出變量，通過對磁鏈和轉速的閉環控制提高定子磁鏈的估計精度，實現了異步電機的無速度傳感器直接轉矩控制策略，仿真結果驗證了該方法的可行性,提高了直接轉矩的控制性能。 Abstract: In order to improve the Direct Torque Control（DTC） system of stator flux estimation accuracy and reduce the current， voltage measurement of random error， a novel method to estimate the speed and rotor position of asynchronous motor based on extended Kalman filter was introduced. EKF was based on d-p axis motor and other motor parameters （state vector: stator current， stator flux linkage， rotor angular speed and position； input: stator voltage； output: staror current). EKF was designed for stator flux and rotor speed estimation in close-loop control. It can improve the estimated accuracy of stator flux. It is possible to estimate the speed and rotor position and implement asynchronous motor drives without position and speed sensors. The simulation results show it is efficient and improves the control performance.

標簽： EKF 異步電機直接轉矩控制系統

上傳時間： 2015-01-02

上傳用戶：qingdou
Fundamental Limits on a Class of Secure

Abstract—In the future communication applications, users may obtain their messages that have different importance levels distributively from several available sources, such as distributed storage or even devices belonging to other users. This scenario is the best modeled by the multilevel diversity coding systems (MDCS). To achieve perfect (information-theoretic) secrecy against wiretap channels, this paper investigates the fundamental limits on the secure rate region of the asymmetric MDCS (AMDCS), which include the symmetric case as a special case. Threshold perfect secrecy is added to the AMDCS model. The eavesdropper may have access to any one but not more than one subset of the channels but know nothing about the sources, as long as the size of the subset is not above the security level. The question of whether superposition (source separation) coding is optimal for such an AMDCS with threshold perfect secrecy is answered. A class of secure AMDCS (S-AMDCS) with an arbitrary number of encoders is solved, and it is shown that linear codes are optimal for this class of instances. However, in contrast with the secure symmetric MDCS, superposition is shown to be not optimal for S-AMDCS in general. In addition, necessary conditions on the existence of a secrecy key are determined as a design guideline.

標簽： Fundamental Limits Secure Class on of

上傳時間： 2020-01-04

上傳用戶：kddlas