針對使用硬件描述語言進行設計存在的問題，提出一種基于FPGA并采用DSP BuilDER作為設計工具的數(shù)字信號處理器設計方法。并按照Matlab/Simulink/DSP BuilDER/QuartusⅡ設計流程，設計了一個12階FIR 低通數(shù)字濾波器，通過Quartus 時序仿真及嵌入式邏輯分析儀SignalTapⅡ硬件測試對設計進行了驗證。結果表明，所設計的FIR 濾波器功能正確，性能良好。
Abstract:
Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP BuilDER as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP BuilDER/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
標簽：
BuilDER
FPGA
DSP
數(shù)字信號處理器
上傳時間：
2013-11-17
上傳用戶：lo25643
