Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUS.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation.
As with the SPI found in MC68HC11 processors the core features programmable clock phase [CPHA] and clock polarity [CPOL]. The core features an 8bit wishbone interface.
Very simple, very small.
LLCR Pin Socket Testing with the Model 3732 High Density Matrix Card
Computer processors (CPUS) today have come a long way from the computer processors of the past. They draw more power, run at lower voltages, and have more pins than ever before.
SL811開發資料_包含源程序_電路圖_芯片資料:SL811HS Embedded USB Host/Slave Controller.The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB peripherals. The SL811HS can interface to devices such as microprocessors, microcontrollers, DSPs, or directly to a variety of buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1.The SL811HS USB Host/Slave Controller incorporates USB Serial Interface functionality along with internal full-/low-speed transceivers.The SL811HS supports and operates in USB full-speed mode at 12 Mbps, or at low-speed 1.5-Mbps mode.The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support to allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUS and many others. Internally,the SL811HS contains a 256-byte RAM data buffer which is used for control registers and data buffer.The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages operate at 3.3 VDC. The I/O interface logic is 5V-tolerant.
一個簡單的ＳＰＩ?。桑泻?，SPI Core Specifications 可以從說明文檔中找到！
The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUS. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires.
FEATURES:
· Compatible with Motorola’s SPI specifications
· Enhanced M68HC11 Serial Peripheral Interface
· 4 entries deep read FIFO
· 4 entries deep write FIFO
· Interrupt generation after 1, 2, 3, or 4 transferred bytes
· 8 bit WISHBONE RevB.3 Classic interface
· Operates from a wide range of input clock frequencies
· Static synchronous design
· Fully synthesizable
This document constitutes the user manual for the YAMON™ ROM monitor.
YAMON (“Yet Another MONitor”) is the ROM monitor used on MIPS Technologies evaluation and reference boards.
The target audience for this document is users of those boards. This would typically be engineers developing hardware
or software including compilers, RTOS and other tools.
Currently, the following boards/CPUS are supported by YAMON :
• Atlas™ with MIPS32 4K™ or MIPS64 5K™ class of CPUS.
• Atlas with QED RM5261® .
• Malta™ with MIPS32 4K or MIPS64 5K class of CPUS.
• Malta with QED RM5261® .
• SEAD™ with MIPS32 4K or MIPS64 5K class of CPUS.
• SEAD-2™ with MIPS32 4K or MIPS64 5K class of CPUS.
The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUS which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache with a write-invalidate policy. The L2 cache is two-way set associative, with a block size of 8 words, and a total capacity of 512 words.
CFE contains the following important features:
* Easy to port to new SB1250/BCM1480 designs
* Initializes CPUS, caches, memory controllers, and peripherals
* Built-in device drivers for SB1250 SOC peripherals
* Several console choices, including serial ports, ROM
emulators, JTAG, etc.
* Environment storage in NV EEPROM, flash, etc.
* Supports big or little endian operation
* Supports 32-bit and 64-bit processors
* Support for network bootstrap. Network protocols supported
include IP,ARP,ICMP,UDP,DHCP,TFTP.
* Support for disk bootstrap.
* Provides an external API for boot loaders and startup programs
* Simple user interface. UI is easy to remove for embedded apps.
The OpenMAX DL (Development Layer) APIs contain a comprehensive set of audio, video, signal processing function primitives which can be implemented and optimized on various CPUS and hardware engines and then used for accelerated codec functionality. API functions target key algorithms in such codecs as H.264, MPEG-4, AAC, MP3, and JPEG.
首先下載軟件，解壓軟件，安裝在程序中找到SEGGER,選里面的J-FLASH，進入界面，剛開始的那個界面可以忽略，不用建project也可以；單擊菜單欄的“Options---Project settings”打開設置，進行jlink配置;正在General選項，選擇“USB”，一般都是默認配置，確認一下即可;然后在CPU選項，選擇芯片型號，先選擇“Device”才能選擇芯片型號，芯片型號，要根據你使用的芯片進行選擇;在Target interface選項 里面選擇SWD模式;首先Target里面選“Connection”連接目標芯片，然后 Target--Auto進行程序燒寫;首先Target里面選擇“Connection”連接目標芯片，然后 Target--Auto進行程序燒寫.SEGGER J-Links are the most widely used line of debug probes available today. They've proven their value for more than 10 years in embedded development. This popularity stems from the unparalleled performance, extensive feature set, large number of supported CPUS, and compatibility with all popular development environments.
