what do you want to? an fox
上傳時(shí)間： 2013-12-25
上傳用戶：yuchunhai1990
Thinking in C++ 2nd edition source code which are all the cores of the book Thinking in C++ second edition.that s the best thing to learn C
標(biāo)簽： Thinking the edition source
上傳時(shí)間： 2013-12-17
上傳用戶：fandeshun
That book tell you how to write code effective and learn it .it s better for your time.
標(biāo)簽： effective better learn write
上傳時(shí)間： 2015-07-23
上傳用戶：himbly
The neclus source code
標(biāo)簽： neclus source code The
上傳時(shí)間： 2015-07-23
上傳用戶：Thuan
工程計(jì)算MATLAB code to calculate the reorthogonalized sine tapers input: N = the length of the time series data to be tapered p = the number of tapers requested I = the gap structure a vector of length N I(t) = 1 if there is data at time t, t=1, ..., N I(t) = 0 if there is a gap at time t output: X = N-by-p vector of the reorthogonalized sine taper
標(biāo)簽： the reorthogonalized calculate MATLAB
上傳時(shí)間： 2013-12-17
上傳用戶：wangyi39
Atmel AT91SAM7S Interrupt example code
標(biāo)簽： Interrupt example Atmel SAM7
上傳時(shí)間： 2013-12-22
上傳用戶：lxm
Data Export成Exce C# Source Code
標(biāo)簽： Export Source Data Code
上傳時(shí)間： 2015-07-24
上傳用戶：fhzm5658
Write Great Code 的第一卷 Understanding the Machine 第一卷用語(yǔ)言無(wú)關(guān)的方式告訴程序員寫出很好的代碼所需要的知識(shí)，而不需要了解具體的匯編語(yǔ)言
標(biāo)簽： Understanding Machine Write Great
上傳時(shí)間： 2013-12-06
上傳用戶：wff
turbo jtag CPLD source code use altera EPM7128S
標(biāo)簽： altera source turbo 7128S
上傳時(shí)間： 2015-07-26
上傳用戶：685
關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標(biāo)簽： investigates implementing pipelines circuits
上傳時(shí)間： 2015-07-26
上傳用戶：CHINA526
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