Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom
instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner
loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II Configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor.
The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
This application note describes how to retrieve user-defined data from Xilinx ConfigurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the Configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
This application note provides a detailed description of the Spartan™-3 Configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the Configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor partial reConfiguration or partial readback.
Express Mode uses an 8-bit wide bus path for fast Configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express Configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express Configuration are described in detail, followed by detailed instructions thatshow how to implement the Configuration circui
This application note shows how to achieve low-cost, efficient serial Configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial Configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan Configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadConfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA Configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to Configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A Configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
This hands-on, one-stop guide delivers the focused, streamlined direction you need to get your Web solutions up and running quickly. Zero in on key ASP.NET Configuration details and techniques using quick-reference tables, lists, coding and more.
Java/J2EE application framework based on [Expert One-on-One J2EE Design and Development] by Rod Johnson. Includes JavaBeans-based Configuration, an AOP framework, declarative transaction management, JDBC and Hibernate support, and a web MVC framework.
