This brief introduce a kind of the framework construction to materialize the system. And an example was given with the discussion on the performence.
標(biāo)簽： construction materialize introduce framework
上傳時(shí)間： 2013-08-17
上傳用戶：ysystc699
implemention of FPGA and DSP linking port, using Asynchronous mode
標(biāo)簽： implemention Asynchronous linking using
上傳時(shí)間： 2013-08-22
上傳用戶：fhjdliu
Cadence Verilog Language and Simulation
標(biāo)簽： Simulation Language Cadence Verilog
上傳時(shí)間： 2013-09-06
上傳用戶：yl1140vista
cadence material includes caden_layout,CADENCE_20Manual,cs5710-layout1x2 and manual
標(biāo)簽： layout manual 5710 and
上傳時(shí)間： 2013-09-10
上傳用戶：kao21
Can convert data file(txt format)to CAD(scr)file,and draw curve!
標(biāo)簽： file convert format curve
上傳時(shí)間： 2013-09-11
上傳用戶：天空說我在
proteus and keil 兩者聯(lián)合實(shí)現(xiàn)Max7221動(dòng)態(tài)顯示，解決一些初學(xué)者對(duì)proteus and keil如何實(shí)現(xiàn)的困惑；
標(biāo)簽： proteus 7221 keil and
上傳時(shí)間： 2013-09-24
上傳用戶：zsjzc
How we make connection with Proteus and the LCD, (project included)
標(biāo)簽： connection Proteus make with
上傳時(shí)間： 2013-09-24
上傳用戶：lihairui42
keil and proteus聯(lián)合演示顯示效果，可實(shí)現(xiàn)音樂的播放，對(duì)初學(xué)者比較有用；很好的例子
標(biāo)簽： proteus keil and 顯示效果
上傳時(shí)間： 2013-09-25
上傳用戶：yangqian
the practice of proteus and avr
標(biāo)簽： practice proteus the and
上傳時(shí)間： 2013-09-29
上傳用戶：tom_man2008
Abstract: Using a wafer-level package (WLP) can reduce the overall size and cost of your solution.However when using a WLP IC, the printed circuit board (PCB) layout can become more complex and, ifnot carefully planned, result in an unreliable design. This article presents some PCB designconsiderations and general recommendations for choosing a 0.4mm- or 0.5mm-pitch WLP for yourapplication.
標(biāo)簽： Considerations Guidelines and Design
上傳時(shí)間： 2013-10-14
上傳用戶：ysystc699
蟲蟲下載站版權(quán)所有 京ICP備2021023401號(hào)-1
