RSA公鑰加密算法基于大整數(shù)因式分解困難這樣的事實(shí)。 選擇兩個(gè)素?cái)?shù)，p，q。（一般p,q選擇很大的數(shù)） 然后計(jì)算 z=p*q f=(p-1)(q-1) 選擇一個(gè)n，使gcd(n,f)=1（gcd代表greatest common Divider,一般n也選擇一個(gè)素?cái)?shù)）， n和z就作為公鑰。 選擇一個(gè)s,0<s<f,滿足n*s ％ f=1，s就作為私鑰。
上傳時(shí)間： 2013-12-14
上傳用戶：wxhwjf
Fast settling-time added to the already conflicting requirements of narrow channel spacing and low phase noise lead to Fractional4 Divider techniques for PLL synthesizers. We analyze discrete "beat-note spurious levels from arbitrary modulus divide sequences including those from classic accumulator methods.
標(biāo)簽： settling-time requirements conflicting already
上傳時(shí)間： 2016-04-14
上傳用戶：liansi
Echo a received character, RX ISR used. Normal mode is LPM0. // USART1 RX interrupt triggers TX Echo. // Baud rate Divider with 1048576hz = 1048576/38400 = ~27.31 (01Bh|03h) // ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz // //* An external watch crystal between XIN & XOUT is required for ACLK
標(biāo)簽： character interrupt received triggers
上傳時(shí)間： 2016-10-31
上傳用戶：rishian
This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assuming a 30Mhz XCLKIN). The clock Divider in the ADC is not used so that the ADC will see the 25Mhz on the HSPCLK. Interrupts are enabled and the EVA is setup to generate a periodic ADC SOC on SEQ1. Two channels are converted, ADCINA3 and ADCINA2.
標(biāo)簽： SYSCLKOUT example divides HSPCLK
上傳時(shí)間： 2014-01-25
上傳用戶：ljt101007
This design uses Common-Emitter Amplifier (Class A) with 2N3904 Bipolar Junction Transistor. Use “Voltage Divider Biasing” to reduce the effects of varying β (= ic / ib) (by holding the Base voltage constant) Base Voltage (Vb) = Vcc * [R2 / (R1 + R2)] Use Coupling Capacitors to separate the AC signals from the DC biasing voltage (which only pass AC signals and block any DC component). Use Bypass Capacitor to maintain the Q-point stability. To determine the value of each component, first set Q-point close to the center position of the load line. (RL is the resistance of the speaker.)
標(biāo)簽： 音頻放大器設(shè)計(jì) 電路圖 英文
上傳時(shí)間： 2020-11-27
上傳用戶：
spi 通信的master部分使用的verilog語言實(shí)現(xiàn)，可以做為你的設(shè)計(jì)參考。module spi_master(rstb,clk,mlb,start,tdat,cdiv,din, ss,sck,dout,done,rdata); input rstb,clk,mlb,start; input [7:0] tdat; //transmit data input [1:0] cdiv; //clock Divider input din; output reg ss; output reg sck; output reg dout; output reg done; output reg [7:0] rdata; //received dataparameter idle=2'b00; parameter send=2'b10; parameter finish=2'b11; reg [1:0] cur,nxt; reg [7:0] treg,rreg; reg [3:0] nbit; reg [4:0] mid,cnt; reg shift,clr;
標(biāo)簽： spi 通信 master verilog
上傳時(shí)間： 2022-02-03
上傳用戶：
The PW2228A is a high efficiency single inductor Buck-Boost converter which can supply theload current up to 1.5A. It provides auto-transition between Buck and Boost Mode. The PW2228Aoperates at 2.4MHz switching frequency in CCM. DC/DC converter operates at Pulse-Skipping Modeat light load. The output voltage is programmable using an external resistor Divider, or is fixed to3.3V internally. The load is disconnected from the VIN during shutdown.The PW2228A is available in TDFN3X3-10 package.
標(biāo)簽： pw2228a
上傳時(shí)間： 2022-02-11
上傳用戶：
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