-
Internal Interrupts are used to respond to asynchronous requests from a certain part of themicrocontroller that needs to be serviced. Each peripheral in the TriCore as well as theBus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPUitself can generate an Interrupt Request.So what is an external Interrupt?An external Interrupt is something alike as the internal Interrupt. The difference is that anexternal Interrupt request is caused by an external event. Normally this would be a pulseon Port0 or Port1, but it can be even a signal from the input buffer of the SSC, indicatingthat a service is requested.The User’s Manual does not explain this aspect in detail so this ApNote will explain themost common form of an external Interrupt request. This ApNote will show that there is aneasy way to react on a pulse on Port0 or Port1 and to create with this impulse an InterruptService Request. Later in the second part of the document, you can find hints on how todebounce impulses to enable the use of a simple switch as the input device.Note: You will find additional information on how to setup the Interrupt System in theApNote “First steps through the TriCore Interrupt System” (AP3222xx)1. It would gobeyond the scope of this document to explain this here, but you will find selfexplanatoryexamples later on.
標簽：
Exter
easy
work
with
上傳時間：
2013-10-27
上傳用戶：zhangyigenius
-
This application note shows how to write an Inter Integrated Circuit bus driver (I²C) for the Philips P90CL301micro-controller.It is not only an example of writing a driver, but it also includes a set of application interface software routines toquickly implement a complete I²C multi-master system application.For specific applications the user will have to make minimal changes in the driver program. Using the drivermeans linking modules to your application software and including a header-file into the application sourceprograms. A small example program of how to use the driver is listed.The driver supports i.a. polled or interrupt driven message handling, slave message transfers and multi-mastersystem applications. Furthermore, it is made suitable for use in conjunction with real time operating systems, likepSOS+.
標簽：
routines
driver
P90
301
上傳時間：
2013-11-23
上傳用戶：weixiao99
-
This application note demonstrates how to write an Inter Integrated Circuit bus driver (I2C) for the XA-S3 16-bitMicrocontroller from Philips Semiconductors.Not only the driver software is given. This note also contains a set of (example) interface routines and a smalldemo application program. All together it offers the user a quick start in writing a complete I2C system applicationwith the PXAS3x.The driver routines support interrupt driven single master transfers. Furthermore, the routines are suitable foruse in conjunction with real time operating systems.
標簽：
software
driver
XA-S
I2C
上傳時間：
2013-11-02
上傳用戶：zw380105939
-
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
標簽：
XAPP
740
AXI
互聯
上傳時間：
2013-11-14
上傳用戶：fdmpy
-
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function
Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標簽：
Transceiver
Virtex
Wizar
GTP
上傳時間：
2013-10-23
上傳用戶：leyesome
-
1.增加的設備支持：
Atmel AT91SAM9Rxx
Cirrus Logic CS7401xx-IQZ
Luminary Micro LM3S576x, LM3S5752, LM3S5747, LM3S573x, LM3S5662, LM3S5652, LM3S5632, LM3S3759, LM3S3749, and LM3S3739
NXP LPC32XX and LPC2460
STMicroelectronics STR912FAZ4X, STR912FAW4X, STR911FAW4X, STR911FAM4X, STR910FAW32, and STR910FAZ32
2.修改了NXP LPC23XX/24XX的頭文件庫
3.增加了ST-LINK II的調試支持
4.增加了對Cortex-M3 內核芯片的RTX Event Viewer 的支持
5.增加了MCBSTM32: STM32 FLASH OPTION BYTES PROGRAMMING
6.增加了ULINK2對Cortex-M3的SWV功能的調試
7.增強了使用GNU在MDK下調試M1,M3,ARM7,ARM9的調試功能（ Using μVision with CodeSourcery GNU ARM Toolchain.）
8.增加了大量經典開發板例程
Boards目錄列表：
├─Embest 深圳市英蓓特公司開發板例程
│ ├─AT91EB40X-40008
│ ├─S3CEB2410
│ ├─ATEBSAM7S
│ ├─LPC22EB06-I
│ ├─LPCEB2000-A
│ ├─LPCEB2000-B
│ ├─LPCEB2000-S
│ ├─str710
│ ├─str711
│ ├─str730
│ ├─str750
│ ├─STR912
│ ├─STM32V100
│ ├─STM32R100
│ ├─ATEB9200
├─ADI ADI半導體的芯片例程
│ ├─ADuC702X
│ └─ADuC712x
├─Atmel Atmel半導體的芯片例程
│ ├─AT91RM9200-EK
│ ├─AT91SAM7A3-EK
│ ├─AT91SAM7S-EK
│ ├─AT91SAM7SE-EK
│ ├─AT91SAM7X-EK
│ ├─AT91SAM9260-EK
│ ├─AT91SAM9261-EK
│ ├─AT91SAM9263-EK
├─Keil Keil公司的開發板例程
│ ├─MCB2100
│ ├─MCB2103
│ ├─MCB2130
│ ├─MCB2140
│ ├─MCB2300
│ ├─MCB2400
│ ├─MCB2900
│ ├─MCBLM3S
│ ├─MCBSTM32
│ ├─MCBSTR7
│ ├─MCBSTR730
│ ├─MCBSTR750
│ └─MCBSTR9
├─Luminary Luminary半導體公司的芯片例程
│ ├─ek-lm3s1968
│ ├─ek-lm3s3748
│ ├─ek-lm3s3768
│ ├─dk-lm3s101
│ ├─dk-lm3s102
│ ├─dk-lm3s301
│ ├─dk-lm3s801
│ ├─dk-lm3s811
│ ├─dk-lm3s815
│ ├─dk-lm3s817
│ ├─dk-lm3s818
│ ├─dk-lm3s828
│ ├─ek-lm3s2965
│ ├─ek-lm3s6965
│ ├─ek-lm3s811
│ └─ek-lm3s8962
├─NXP NXP半導體公司的芯片例程
│ ├─LH79524
│ ├─LH7A404
│ └─SJA2510
├─OKI OKI半導體公司的芯片例程
│ ├─ML674000
│ ├─ML67Q4003
│ ├─ML67Q4051
│ ├─ML67Q4061
│ ├─ML67Q5003
│ └─ML69Q6203
├─Samsung Samsung半導體公司的芯片例程
│ ├─S3C2440
│ ├─S3C44001
│ └─S3F4A0K
├─ST ST半導體公司的芯片例程
│ ├─CQ-STARM2
│ ├─EK-STM32F
│ ├─STM32F10X_EVAL
│ ├─STR710
│ ├─STR730
│ ├─STR750
│ ├─STR910
│ └─STR9_DONGLE
├─TI TI半導體公司的芯片例程
│ ├─TMS470R1A256
│ └─TMS470R1B1M
├─Winbond Winbond半導體公司的芯片例程
│ └─W90P710
└─ ...
標簽：
realview
mdk
3.2
上傳時間：
2013-10-13
上傳用戶：zhangliming420
-
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI).
The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT).
The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset.
If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on.
In this example the system is clocked by the HSE(8MHz).
標簽：
V100
STM
100
32V
上傳時間：
2013-11-11
上傳用戶：gundamwzc
-
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
標簽：
XAPP
740
AXI
互聯
上傳時間：
2013-11-23
上傳用戶：shen_dafa
-
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function
Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標簽：
Transceiver
Virtex
Wizar
GTP
上傳時間：
2013-10-20
上傳用戶：dave520l
-
A CCITT-16 CRC calculator. The source contains both the calculated (smaller but slower) version, and the table driven (faster but larger) version.
標簽：
calculator
calculated
contains
smaller
上傳時間：
2015-01-13
上傳用戶：s363994250
