The core voltages for FPGAs are moving lower as a resultof advances in the fabrication process. The newest FPGAfamily from Altera, the Stratix® II, now requires a corevoltage of 1.2V and the Stratix, Stratix GX, HardCopy®Stratix and CycloneTM families require a core voltage of1.5V. This article discusses how to power the core and I/Oof low voltage FPGAs using the latest step-down switchmode controllers from Linear Technology Corporation.
Many complex systems—such as telecom equipment,memory modules, optical systems, networking equipment,servers and base stations—use FPGAs and otherdigital ICs that require multiple voltage rails that muststart up and shut down in a specific order, otherwise theICs can be damaged. The LTC®2924 is a simple andcompact solution to power supply sequencing in a 16-pinSSOP package (see Figures 1 and 2).
In a recent discussion with a system designer, the requirementfor his power supply was to regulate 1.5Vand deliver up to 40A of current to a load that consistedof four FPGAs. This is up to 60W of power that must bedelivered in a small area with the lowest height profi lepossible to allow a steady fl ow of air for cooling. Thepower supply had to be surface mountable and operateat high enough effi ciency to minimize heat dissipation.He also demanded the simplest possible solution so histime could be dedicated to the more complex tasks. Asidefrom precise electrical performance, this solution had toremovethe heat generated during DC to DC conversionquickly so that the circuit and the ICs in the vicinity do notoverheat. Such a solution requires an innovative designto meet these criteria:
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard aresketchy. And once an entity develops a process thatachieves compliance, the details of how compliancewas achieved become part of the intellectualproperty of that entity. This white paper focuses onthe details of developing a DO-254 compliantprocess for the design of FPGAs.
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for 100K gate-level units, any design with programmablelogic has a readily available 8- or 16-bit processor costingless than 75 cents and 32-bit processor for less than $1.50.
