Nios II軟件構(gòu)建工具入門(mén) The Nios® II Software Build Tools (SBT) allows you to construct a wide variety of complex embedded software systems using a command-line interface. From this interface, you can execute Software Built Tools command utilities, and use scripts other tools) to combine the command utilities in many useful ways. This chapter introduces you to project creation with the SBT at the command line This chapter includes the following sections: ■ “Advantages of Command-Line Software Development” ■ “Outline of the Nios II SBT Command-Line Interface” ■ “Getting Started in the SBT Command Line” ■ “Software Build Tools Scripting Basics” on page 3–8
上傳時(shí)間： 2013-11-15
上傳用戶：nanxia
使用Nios II軟件構(gòu)建工具 This chapter describes the Nios® II Software Build Tools (SBT), a set of utilities and scripts that creates and builds embedded C/C++ application projects, user library projects, and board support packages (BSPs). The Nios II SBT supports a repeatable, scriptable, and archivable process for creating your software product. You can invoke the Nios II SBT through either of the following user interfaces: ■ The Eclipse™ GUI ■ The Nios II Command Shell The purpose of this chapter is to make you familiar with the internal functionality of the Nios II SBT, independent of the user interface employed.
上傳時(shí)間： 2013-10-12
上傳用戶：china97wan
通過(guò)以太網(wǎng)遠(yuǎn)程配置Nios II 處理器 應(yīng)用筆記 Firmware in embedded hardware systems is frequently updated over the Ethernet. For embedded systems that comprise a discrete microprocessor and the devices it controls, the firmware is the software image run by the microprocessor. When the embedded system includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as part of the FPGA image—and the software that the Nios II processor runs, in a single remote configuration session.
標(biāo)簽： Nios 遠(yuǎn)程 處理器 應(yīng)用筆記
上傳時(shí)間： 2013-11-22
上傳用戶：chaisz
面向Eclips的Nios II軟件構(gòu)建工具手冊(cè) The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the Eclipse™ framework and the Eclipse C/C++ development toolkit (CDT) plugins. The Nios II SBT for Eclipse provides a consistent development platform that works for all Nios II embedded processor systems. You can accomplish all Nios II software development tasks within Eclipse, including creating, editing, building, running, debugging, and profiling programs.
上傳時(shí)間： 2013-11-02
上傳用戶：瓦力瓦力hong
怎樣使用Nios II處理器來(lái)構(gòu)建多處理器系統(tǒng) Chapter 1. Creating Multiprocessor Nios II Systems Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1 Benefits of Hierarchical Multiprocessor Systems . . . . . . . . . . . . . . . 1–2 Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Multiprocessor Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . 1–3 Hardware Designs for Peripheral Sharing . . . . . . . . . . . .. . . . . . . . 1–3 Autonomous Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Multiprocessors that Share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4 Sharing Peripherals in a Multiprocessor System . . . . . . . . . . . . . . . . . 1–4 Sharing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 The Hardware Mutex Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7 Sharing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8 Overlapping Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 Software Design Considerations for Multiple Processors . . .. . . . . 1–9 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Boot Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13 Debugging Nios II Multiprocessor Designs . . . . . . . . . . . . . . . . 1–15 Design Example: The Dining Philosophers’ Problem . . . . .. . . 1–15 Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16 Installation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Creating the Hardware System . . . . . . . . . . . . . . .. . . . . . 1–17 Getting Started with the multiprocessor_tutorial_start Design Example 1–17 Viewing a Philosopher System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18 Philosopher System Pipeline Bridges . . . . . . . . . . . . . . . . . . . . . 1–19 Adding Philosopher Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21 Connecting the Philosopher Subsystems . . . . . . . . . . . . .. . . . . 1–22 Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27 Generating and Compiling the System . . . . . . . . . . . . . . . . . .. 1–28
上傳時(shí)間： 2013-11-21
上傳用戶：lo25643
使用Nios II緊耦合存儲(chǔ)器教程 Chapter 1. Using Tightly Coupled Memory with the Nios II Processor Reasons for Using Tightly Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . 1–1 Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Guidelines for Using Tightly Coupled Memory . . . .. . . . . . . . 1–2 Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Software Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1–3 Locating Functions in Tightly Coupled Memory . . . . . . . . . . . . . 1–3 Tightly Coupled Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Dual Port Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 1–5 Building a Nios II System with Tightly Coupled Memory . . . . . . . . . . . 1–5
上傳時(shí)間： 2013-10-13
上傳用戶：黃婷婷思密達(dá)
Nios II 軟件開(kāi)發(fā)人員手冊(cè)中的緩存和緊耦合存儲(chǔ)器部分 Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II architecture provides facilities to perform the following actions:
標(biāo)簽： Nios 軟件開(kāi)發(fā) 存儲(chǔ)器
上傳時(shí)間： 2013-10-25
上傳用戶：蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)
Nios II內(nèi)核詳細(xì)實(shí)現(xiàn)
上傳時(shí)間： 2015-01-01
上傳用戶：源碼3
FPGA&SOPC簡(jiǎn)明教程
標(biāo)簽： FPGA SOPC 簡(jiǎn)明教程
上傳時(shí)間： 2013-10-23
上傳用戶：woshiayin
《Altera FPGA工程師成長(zhǎng)手冊(cè)》以altera公司的fpga為例，由淺入深，全面、系統(tǒng)地詳細(xì)講述了基于可編程邏輯技術(shù)的設(shè)計(jì)方法。《Altera FPGA工程師成長(zhǎng)手冊(cè)》講解時(shí)穿插了大量典型實(shí)例，便于讀者理解和演練。另外，為了幫助讀者更好地學(xué)習(xí)，《Altera FPGA工程師成長(zhǎng)手冊(cè)》提供了配套語(yǔ)音教學(xué)視頻，這些視頻和《Altera FPGA工程師成長(zhǎng)手冊(cè)》源代碼一起收錄于《Altera FPGA工程師成長(zhǎng)手冊(cè)》配書(shū)光盤(pán)中。 《Altera FPGA工程師成長(zhǎng)手冊(cè)》涉及面廣，從基本的軟件使用到一般電路設(shè)計(jì)，再到nios ⅱ軟核處理器的設(shè)計(jì)，幾乎涉及fpga開(kāi)發(fā)設(shè)計(jì)的所有知識(shí)。具體內(nèi)容包括：eda開(kāi)發(fā)概述、altera quartus ii開(kāi)發(fā)流程、altera quartus ii開(kāi)發(fā)向?qū)Аhdl語(yǔ)言、基本邏輯電路設(shè)計(jì)、宏模塊、lpm函數(shù)應(yīng)用、基于fpga的dsp開(kāi)發(fā)設(shè)計(jì)、sopc系統(tǒng)構(gòu)架、soc系統(tǒng)硬件開(kāi)發(fā)、sopc系統(tǒng)軟件開(kāi)發(fā)、nios ii常用外設(shè)、logiclock優(yōu)化技術(shù)等。
標(biāo)簽： Altera FPGA 清華大學(xué) 工程師
上傳時(shí)間： 2015-01-01
上傳用戶：123啊
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