The main objective of this book is to present all the relevant informationrequired for RF and micro-wave power amplifier design includingwell-known and novel theoretical approaches and practical design techniquesas well as to suggest optimum design approaches effectively combininganalytical calculations and computer-aided design. This bookcan also be very useful for lecturing to promote the analytical way ofthinking with practical verification by making a bridge between theoryand practice of RF and microwave engineering. As it often happens, anew result is the well-forgotten old one. Therefore, the demonstrationof not only new results based on new technologies or circuit schematicsis given, but some sufficiently old ideas or approaches are also introduced,that could be very useful in modern practice or could contributeto appearance of new ideas or schematic techniques.
標(biāo)簽： Amplifier Microwave Design Power
上傳時(shí)間： 2013-12-22
上傳用戶：vodssv
The information in this specification is subject to change without notice.Use of this specification for product design requires an executed license agreement from the CompactFlashAssociation.The CompactFlash Association shall not be liable for technical or editorial errors or omissions contained herein; norfor incidental or consequential damages resulting from the furnishing, performance, or use of this material.All parts of the CompactFlash Specification are protected by copyright law and all rights are reserved. Thisdocumentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to anyelectronic medium or machine readable form without prior consent, in writing, from the CompactFlash Association.The CFA logo is a trademark of the CompactFlash Association.Product names mentioned herein are for identification purposes only and may be trademarks and/or registeredtrademarks of their respective companies.© 1998-99, CompactFlash Association. All rights reserved.
標(biāo)簽： 技術(shù)資料
上傳時(shí)間： 2013-10-08
上傳用戶：stewart·
ExpressPCB 是一款免費(fèi)的PCB設(shè)計(jì)軟件，簡(jiǎn)單實(shí)使。可以畫雙層板。 Our Free PCB software is a snap to learn and use. For the first time, designing circuit boards is simple for the beginner and efficient for the professional. Our board manufacturing service makes top quality two and four layer PCBs. Use our MiniBoard service and pay only $51 for three boards (plus $8 shipping).
標(biāo)簽： ExpressPCB PCB 設(shè)計(jì)軟件
上傳時(shí)間： 2013-11-15
上傳用戶：lchjng
ExpressPCB 是一款免費(fèi)的PCB設(shè)計(jì)軟件，簡(jiǎn)單實(shí)使。可以畫雙層板。 Our Free PCB software is a snap to learn and use. For the first time, designing circuit boards is simple for the beginner and efficient for the professional. Our board manufacturing service makes top quality two and four layer PCBs. Use our MiniBoard service and pay only $51 for three boards (plus $8 shipping).
標(biāo)簽： ExpressPCB PCB 設(shè)計(jì)軟件
上傳時(shí)間： 2013-10-09
上傳用戶：1047385479
本文簡(jiǎn)單探討了verilog HDL設(shè)計(jì)中的可綜合性問(wèn)題，適合HDL初學(xué)者閱讀 用組合邏輯實(shí)現(xiàn)的電路和用時(shí)序邏輯實(shí)現(xiàn)的 電路要分配到不同的進(jìn)程中。 不要使用枚舉類型的屬性。 Integer應(yīng)加范圍限制。 通常的可綜合代碼應(yīng)該是同步設(shè)計(jì)。 避免門級(jí)描述，除非在關(guān)鍵路徑中。
標(biāo)簽： HDL 綜合設(shè)計(jì)
上傳時(shí)間： 2013-11-18
上傳用戶：swaylong
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.
標(biāo)簽： Synplicity Machine Verilog Design
上傳時(shí)間： 2013-10-20
上傳用戶：蒼山觀海
UART 4 UART參考設(shè)計(jì)，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
標(biāo)簽： UART Xilinx VHDL 參考設(shè)計(jì)
上傳時(shí)間： 2013-11-02
上傳用戶：18862121743
各種功能的計(jì)數(shù)器實(shí)例（VHDL源代碼）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;
標(biāo)簽： VHDL 計(jì)數(shù)器 源代碼
上傳時(shí)間： 2013-10-09
上傳用戶：松毓336
Frequently, voltage reference stability and noise defi nemeasurement limits in instrumentation systems. In particular,reference noise often sets stable resolution limits.Reference voltages have decreased with the continuingdrop in system power supply voltages, making referencenoise increasingly important. The compressed signalprocessing range mandates a commensurate reductionin reference noise to maintain resolution. Noise ultimatelytranslates into quantization uncertainty in A to D converters,introducing jitter in applications such as scales, inertialnavigation systems, infrared thermography, DVMs andmedical imaging apparatus. A new low voltage reference,the LTC6655, has only 0.3ppm (775nV) noise at 2.5VOUT.Figure 1 lists salient specifi cations in tabular form. Accuracyand temperature coeffi cient are characteristic ofhigh grade, low voltage references. 0.1Hz to 10Hz noise,particularly noteworthy, is unequalled by any low voltageelectronic reference.
標(biāo)簽： 低噪聲 電壓基準(zhǔn) 噪聲測(cè)量
上傳時(shí)間： 2013-10-30
上傳用戶：wxhwjf
隨著總線和接口技術(shù)的發(fā)展，在工業(yè)場(chǎng)合如何更加可靠、快速、便捷地進(jìn)行數(shù)據(jù)傳輸成為該領(lǐng)域通信的研究重點(diǎn)之一。而USB技術(shù)以其高速、可靠、通用性強(qiáng)等一系列特點(diǎn)在過(guò)去的十多年時(shí)間里發(fā)展迅猛，而USB OTG技術(shù)的誕生，使得兩USB設(shè)備在沒(méi)有PC參與的情況下進(jìn)行數(shù)據(jù)傳輸成為可能。本文通過(guò)搭建以16位微處理器MSP430F149為核心控制芯片、ISPl362為USB接口芯片的硬件平臺(tái)，分別實(shí)現(xiàn)了USB部分主機(jī)和從機(jī)功能，使之能進(jìn)行USB數(shù)據(jù)的存儲(chǔ)與交換。本文完成以下工作：首先，認(rèn)真研究USB協(xié)議，深入理解USB通信的基本概念和傳輸方式等內(nèi)容。仔細(xì)分析USB Mass Storage類協(xié)議，并討論了采用BULK-ONLY傳輸實(shí)現(xiàn)Mass Storage類協(xié)議的方法，并對(duì)SCSI指令集等進(jìn)行了深入的剖析。其次，根據(jù)要求，設(shè)計(jì)出由控制、接口、數(shù)據(jù)存儲(chǔ)、過(guò)流保護(hù)與供電切換電路等硬件模塊組成的系統(tǒng)，在ALTIUM 2004軟件上完成原理圖的設(shè)計(jì)和PCB圖的布局、布線，并完成硬件調(diào)試工作。再次，在已構(gòu)建的硬件平臺(tái)上，針對(duì)ISPl362 USB接口芯片的主／從機(jī)功能，分別設(shè)計(jì)了USB主機(jī)和從機(jī)的固件程序。利用IAR Workbench、BusHound等軟件進(jìn)行固件程序的調(diào)試，最終USB主機(jī)可對(duì)u盤進(jìn)行檢測(cè)、識(shí)別與配置；USB設(shè)備實(shí)現(xiàn)了USB設(shè)備的基本功能，能夠被Windows XP操作系統(tǒng)識(shí)別，與PC機(jī)之間實(shí)現(xiàn)數(shù)據(jù)的批量傳輸。最后，用DriverWorks軟件包的Driver Wizard生成驅(qū)動(dòng)程序框架，并利用Windows DDK和vc++等軟件進(jìn)行驅(qū)動(dòng)程序的編譯，最終生成基于Windows操作系統(tǒng)的WDM型USB設(shè)備驅(qū)動(dòng)程序。通過(guò)對(duì)USB通信協(xié)議的研究，本人成功地構(gòu)建了以MsP430F149和ISPl362為核心的硬件試驗(yàn)平臺(tái)，并在此平臺(tái)上進(jìn)行USB主機(jī)、從機(jī)通信試驗(yàn)。經(jīng)測(cè)試表明，PC機(jī)能檢測(cè)、識(shí)別、讀寫USB設(shè)備，其讀取與寫入速度分別為560KB／s和312Ⅺ玳。而主機(jī)能識(shí)別、配置接入的U盤。關(guān)鍵詞：USB主機(jī)、USB從機(jī)、MSI'430F149、ISPl362、BuR-Only傳輸
上傳時(shí)間： 2013-10-11
上傳用戶：淺言微笑
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