PSPICE是由SPICE（Simulation Program with INTEGRATED Circuit Emphasis）發(fā)展而來的用于微機(jī)系列的通用電路分析程序。于1972年由美國(guó)加州大學(xué)伯克利分校的計(jì)算機(jī)輔助設(shè)計(jì)小組利用FORTRAN語言開發(fā)而成，主要用于大規(guī)模集成電路的計(jì)算機(jī)輔助設(shè)計(jì)。
標(biāo)簽： Pspice 仿真
上傳時(shí)間： 2015-12-04
上傳用戶：kendisc
The TAS3204 is a highly-INTEGRATED audio system-on-chip (SOC) consisting of a fully-programmable, 48-bit digital audio processor, a 3:1 stereo analog input MUX, four ADCs, four DACs, and other analog functionality. The TAS3204 is programmable with the graphical PurePath Studio? suite of DSP code development software. PurePath Studio is a highly intuitive, drag-and-drop environment that minimizes software development effort while allowing the end user to utilize the power and flexibility of the TAS3204’s digital audio processing core. TAS3204 processing capability includes speaker equalization and crossover, volume/bass/treble control, signal mixing/MUXing/splitting, delay compensation, dynamic range compression, and many other basic audio functions. Audio functions such as matrix decoding, stereo widening, surround sound virtualization and psychoacoustic bass boost are also available with either third-party or TI royalty-free algorithms. The TAS3204 contains a custom-designed, fully-programmable 135-MHz, 48-bit digital audio processor. A 76-bit accumulator ensures that the high precision necessary for quality digital audio is maintained during arithmetic operations. Four differential 102 dB DNR ADCs and four differential 105 dB DNR DACs ensure that high quality audio is maintained through the whole signal chain as well as increasing robustness against noise sources such as TDMA interference. The TAS3204 is composed of eight functional blocks: Clocking System Digital Audio Interface Analog Audio Interface Power supply Clocks, digital PLL I2C control interface 8051 MCUcontroller Audio DSP – digital audio processing 特性 Digital Audio Processor Fully Programmable With the Graphical, Drag-and-Drop PurePath Studio? Software Development Environment 135-MHz Operation 48-Bit Data Path With 76-Bit Accumulator Hardware Single-Cycle Multiplier (28 × 48)
上傳時(shí)間： 2016-05-06
上傳用戶：fagong
1．軟件安裝步驟 a)運(yùn)行光盤中客戶軟件\CCS5000 CCS2.20\CCS2.2\SETUP.EXE，進(jìn)入引導(dǎo)界面； b)選擇Install下的Code Composer Studio進(jìn)入安裝界面； c)按照默認(rèn)的方式安裝，裝在C:\ti下。 d)安裝軟件補(bǔ)丁：運(yùn)行光盤客戶軟件\c5000ccs2.20\CCS FOR C5000-補(bǔ)丁\C5000-2.20.00-FULL-to-C5000-2.20.18-FULL.EXE,進(jìn)入安裝界面,然后按照默認(rèn)的方式安裝即可。 e)重新啟動(dòng)計(jì)算機(jī)，按DEL鍵進(jìn)入CMOS的設(shè)置界面CMOS SETUP UTILITY，將INTEGRATED Peripherals中的Onboard Paralell Port改為378/IRQ，Parrallel Port Mode改為EPP，保存退出。 f)進(jìn)入windows后會(huì)出現(xiàn)“CCS 2(‘ C5000) ”、 “Setup CCS 2(‘ C5000) ”兩個(gè)圖標(biāo)。
標(biāo)簽： 激活
上傳時(shí)間： 2017-01-03
上傳用戶：jmw8637
A major societal challenge for the decades to come will be the delivery of effective medical services while at the same time curbing the growing cost of healthcare. It is expected that new concepts-particularly electronically assisted healthcare will provide an answer. This will include new devices, new medical services as well as networking. On the device side, impressive innovation has been made possible by micro- and nanoelectronics or CMOS INTEGRATED Circuits. Even higher accuracy and smaller form factor combined with reduced cost and increased convenience of use are enabled by incorporation of CMOS IC design in the realization of biomedical systems. The compact hearing aid devices and current pacemakers are good examples of how CMOS ICs bring about these new functionalities and services in the medical field. Apart from these existing applications, many researchers are trying to develop new bio-medical solutions such as Artificial Retina, Deep Brain Stimulation, and Wearable Healthcare Systems. These are possible by combining the recent advances of bio-medical technology with low power CMOS IC technology.
上傳時(shí)間： 2017-02-06
上傳用戶：linyj
I2C（Inter－INTEGRATED Circuit）總線是由PHILIPS公司開發(fā)的兩線式串行總線，用于連接微控制器及其外圍設(shè)備。是微電子通信控制領(lǐng)域廣泛采用的一種總線標(biāo)準(zhǔn)。
上傳時(shí)間： 2017-05-10
上傳用戶：simon_edthorek
The 4.0 kbit/s speech codec described in this paper is based on a Frequency Domain Interpolative (FDI) coding technique, which belongs to the class of prototype waveform Interpolation (PWI) coding techniques. The codec also has an INTEGRATED voice activity detector (VAD) and a noise reduction capability. The input signal is subjected to LPC analysis and the prediction residual is separated into a slowly evolving waveform (SEW) and a rapidly evolving waveform (REW) components. The SEW magnitude component is quantized using a hierarchical predictive vector quantization approach. The REW magnitude is quantized using a gain and a sub-band based shape. SEW and REW phases are derived at the decoder using a phase model, based on a transmitted measure of voice periodicity. The spectral (LSP) parameters are quantized using a combination of scalar and vector quantizers. The 4.0 kbits/s coder has an algorithmic delay of 60 ms and an estimated floating point complexity of 21.5 MIPS. The performance of this coder has been evaluated using in-house MOS tests under various conditions such as background noise. channel errors, self-tandem. and DTX mode of operation, and has been shown to be statistically equivalent to ITU-T (3.729 8 kbps codec across all conditions tested.
標(biāo)簽： frequency-domain interpolation performance Design kbit_s speech coder based and of
上傳時(shí)間： 2018-04-08
上傳用戶：kilohorse
Description The L9352B is an INTEGRATED quad low-side power switch to drive inductive loads like valves used in ABS systems. Two of the four channels are current regulators with current range from 0 mA to 2.25 A. All channels are protected against fail functions. They are monitored by a status output.
標(biāo)簽： L9352B
上傳時(shí)間： 2019-03-27
上傳用戶：guaixiaolong
集成電路（INTEGRATED circuit）是一種微型電子器件或部件。采用一定的工藝，把一個(gè)電路中所需的晶體管、電阻、電容和電感等元件及布線互連一起，制作在一小塊或幾小塊半導(dǎo)體晶片或介質(zhì)基片上，然后封裝在一個(gè)管殼內(nèi)，成為具有所需電路功能的微型結(jié)構(gòu)。
上傳時(shí)間： 2019-06-14
上傳用戶：ljianboo
Emerging technologies such as WiFi and WiMAX are profoundly changing the landscape of wireless broadband. As we evolve into future generation wireless networks, a primary challenge is the support of high data rate, INTEGRATED multi- media type traffic over a unified platform. Due to its inherent advantages in high-speed communication, orthogonal frequency division multiplexing (OFDM) has become the modem of choice for a number of high profile wireless systems (e.g., DVB-T, WiFi, WiMAX, Ultra-wideband).
標(biāo)簽： Broadband Wireless Networks
上傳時(shí)間： 2020-05-26
上傳用戶：shancjb
The design and manufacturing of wireless radio frequency (RF) transceivers has developed rapidly in recent ten yeas due to rapid development of RF INTEGRATED circuits and the evolution of high-speed digital signal processors (DSP). Such high speed signal processors, in conjunction with the development of high resolution analog to digital converters and digital to analog converters, has made it possible for RF designers to digitize higher intermediate frequencies, thus reducing the RF section and enhancing the overall performance of the RF section.
標(biāo)簽： Transceivers Wireless Digital
上傳時(shí)間： 2020-05-27
上傳用戶：shancjb
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