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Low-Density

5GNR信道編碼研究.pdf

5GNR信道編碼研究，信道編碼是 5G 的關鍵技術之一，描述了 5G 新空口（NR——New Radio Access）的低密度奇偶校驗碼（LDPCC——Low Density Parity Check Codes）和極化碼（Polar Codes）的關鍵技術；通過仿真，比較了5G NR的信道編碼方案與 4G LTE信道編碼方案的性能。另外，還比較了這2代信道編碼技術的復雜度和吞吐量。

標簽： 信道編碼

上傳時間： 2022-06-30

上傳用戶：
MAX2691 L2 Band GPS Low-Noise Amplifier

The MAX2691 low-noise amplifier (LNA) is designed forGPS L2 applications. Designed in Maxim’s advancedSiGe process, the device achieves high gain andlow noise figure while maximizing the input-referred 1dBcompression point and the 3rd-order intercept point. TheMAX2691 provides a high gain of 17.5dB and sub 1dBnoise figure.

標簽： Amplifier Low-Noise 2691 Band

上傳時間： 2014-12-04

上傳用戶：zaocan888
Achieving High Power Density Designs

Achieving High Power Density Designs

標簽： Achieving Density Designs Power

上傳時間： 2013-10-12

上傳用戶：qazxsw
DN457寬輸入電壓范圍同步降壓穩壓器

The LTC®3610 is a high power monolithic synchronousstep-down DC/DC regulator that can deliver up to 12Aof continuous output current from a 4V to 24V (28Vmaximum) input supply. It is a member of a high currentmonolithic regulator family (see Table 1) that featuresintegrated low RDS(ON) N-channel top and bottomMOSFETs. This results in a high effi ciency and highpower density solution with few external components.This regulator family uses a constant on-time valleycurrent mode architecture that is capable of operatingat very low duty cycles at high frequency and with veryfast transient response. All are available in low profi le(0.9mm max) QFN packages.

標簽： 457 DN 寬同步降壓

上傳時間： 2013-11-07

上傳用戶：moerwang
at89c52 pdf

The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded controlapplications.

標簽： 89c c52 at

上傳時間： 2013-11-10

上傳用戶：1427796291
Analog Solutions for Xilinx FPGAs

Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables

標簽： Solutions Analog Xilinx FPGAs

上傳時間： 2013-11-01

上傳用戶：a67818601
Analog Solutions for Altera FPGAs

Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)

標簽： Solutions Analog Altera FPGAs

上傳時間： 2013-11-08

上傳用戶：蟲蟲蟲蟲蟲蟲
Analog Solutions for Altera FPGAs

Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)

標簽： Solutions Analog Altera FPGAs

上傳時間： 2013-10-27

上傳用戶：fredguo
Analog Solutions for Xilinx FPGAs

Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables

標簽： Solutions Analog Xilinx FPGAs

上傳時間： 2013-11-07

上傳用戶：suicone
16kb/s Low Delay CELP 算法

16kb/s Low Delay CELP 算法

標簽： Delay CELP Low 16

上傳時間： 2015-01-03

上傳用戶：huangld