針對目前汽車追尾事件頻發問題，提出一種防汽車車前和車后追尾的安全裝置設計。該設計以高性能、低功耗的8位AVR微處理器ATmega8L為核心，結合霍爾式車速傳感器、激光雷達測距裝置和MMA7260QT加速度傳感器，能夠兼顧車前和車后，摒棄以往設計中只考慮車前或車后單一性缺點，尤其適用于高速、夜晚或新手行車。
Abstract:
Aiming at the high frequency of vehicle rear-end collision，a safe device design of anti-vehicle rear-end collision is presented.In the design，the high-performance，low-power8-bit AVR Microprocessor ATmega8L is utilized as a core combined with Hall-type speed sensor，laser-radar ranging devices and the acceleration sensor MMA7260QT.The design considers both the front and back of a car，and overcomes the drawbacks of former designs in which only the front or the back of the car is considered，so it is especially suitable for high-speed，night or the beginner’s driving.
實時時鐘是微機保護裝置的重要部件，在討論PCF8583結構與功能的基礎上，提出采用dsPIC33F系列微處理器與串行I2C時鐘PCF8583的接口設計方案，給出了相應的接口電路與軟件流程。該設計方案結構簡單，可靠性高，開發周期短，具有一定的實用與參考價值。所設計的微機保護裝置已投入現場運行，效果良好。
Abstract:
Real-time clock chip is an important part in microcomputer protection device.Based on discussing the structure and function of PCF8583，a new interface scheme which uses dsPIC33F Microprocessor and serial clock chip（I2C）PCF8583is proposed.The method of the circuit design and the main software flow are introduced in this paper.The scheme has simple structure，higher reliability and shorter exploitation cycle，so has definite practicality or reference value.The microcomputer protection device has been put into operation with better effects.
數字信號處理器dsPIC33F集多通道高精度A/D轉換、多通訊模式、看門狗、CMOS Flash技術等于一體，其內部可完成所有數據操作，實現總線不出芯片技術。將該處理器應用于微機保護裝置，提出基于dsPIC33F微處理器的微機保護裝置的設計方案，給出相應的接口電路與軟件流程。該設計方案結構簡單，性價比及可靠性高，開發周期短，具有一定的實用推廣價值。所研制的微機保護裝置現場運行效果良好。
Abstract:
The dsPIC33F Microprocessor has a plentiful interior resource which contains multi-channel，high precision A/D converters，multi-communication module，watchdog，CMOS Flash technology，and so on.All data manipulations is accomplished interiorly.What is more，it makes the technology that bus does not go beyond the chip comes into practice.The paper put forwards a design scheme based on dsPIC33F Microprocessor.The scheme has the advantages of simple structure，high reliability and shortened exploitation cycle.What is more，it has definite practicality and reference.The microcomputer protection device has been put into operation with excellent effects.
主要介紹了以PIC18F2480單片機為處理器，基于可編程多路開關檢測接口器件MC33993實現的車用多路開關檢測接口電路的設計。該設計克服了以往基于分立元件的檢測接口電路的弊端，簡化了接口電路設計，保證了車用開關工作的可靠性和安全性。
Abstract:
The design of automotive multiple switch detection interface circuit based on MC33993 is introduced mainly which adopts PIC18F2480 single chip Microprocessor.This circuit overcomes shortage of traditional design which contains many schism elements, and the application of MC33993 also predigests the whole design of interface circuit and guarantees the dependability and security of the switch.
Bootloader是微處理器上電時運行的第一段代碼，它可以通過通信接口實現對微處理器內部應用程序的更新升級，為網絡化嵌入式產品的應用程序升級帶來極大的便利。由于目前沒有統一嵌入式系統的Bootloader。基于NEC 78K0系列單片機自編程原理，設計出一個適用于78K0/Fx2系列單片機的Bootloader，并能夠通過單片機串口在線升級應用程序。
Abstract:
Bootloader is the first piece of code executed after Microprocessor startup. It makes the embedded product’s firmware update conveniently through communication interface. However， no unified bootloader is available for all kinds of Microprocessor products. Based on the principle of self-programming NEC 78K0s’ series， a useful Bootloader which is suitable for 78K0/Fx2s’ series MCU is designed，the design can update the application through serial ports.
匯編器在微處理器的驗證和應用中舉足輕重，如何設計通用的匯編器一直是研究的熱點之一。本文提出了一種開放式的匯編器系統設計思想，在匯編語言與機器語言間插入中間代碼CMDL（code mapping description language）語言，打破匯編語言與機器語言的直接映射關系，由此建立起一套描述匯編語言與機器語言的開放式映射體系。基于此開放式映射體系開發了一套匯編器系統，具有較高層次上的通用性和可移植性。【關鍵詞】指令集，CMDL，匯編器，開放式
Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of Microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【關鍵詞】instruction set, symbol table, assembler, lexical analysis, retargetability
本文依據集成電路設計方法學，探討了一種基于標準Intel 8086 微處理器的單芯片計算機平臺的架構。研究了其與SDRAM，8255 并行接口等外圍IP 的集成，并在對AMBA協議和8086 CPU分析的基礎上，采用遵從AMBA傳輸協議的系統總線代替傳統的8086 CPU三總線結構，搭建了基于8086 IP 軟核的單芯片計算機系統，并實現了FPGA 功能演示。關鍵詞：微處理器； SoC；單芯片計算機；AMBA 協議
Design of 8086 CPU Based Computer-on-a-chip System（School of Electrical Engineering and Automation, Heifei University of Technology, Hefei, 230009,China）Abstract: According to the IC design methodology, this paper discusses the design of one kind of Computer-on-a-chip system architecture, which is based on the standard Intel8086 Microprocessor,investigates how to integrate the 8086 CPU and peripheral IP such as, SDRAM controller, 8255 PPI etc. Based on the analysis of the standard Intel8086 Microprocessor and AMBA Specification,the Computer-on-a-chip system based on 8086 CPU which uses AMBA bus instead of traditional three-bus structure of 8086 CPU is constructed, and the FPGA hardware emulation is fulfilled.Key words: Microprocessor; SoC; Computer-on-a-chip; AMBA Specification
In this document, the term Ô60xÕ is used to denote a 32-bit Microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 Microprocessors. Note that this does not include the PowerPC 602ª Microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªMicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC Microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded Microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ Microprocessor.
