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Multiplier

  • Wallace Tree Multiplier in VHDL for 4bit operation fully using structural language

    Wallace Tree Multiplier in VHDL for 4bit operation fully using structural language

    標簽: Multiplier structural operation language

    上傳時間: 2014-01-04

    上傳用戶:hfmm633

  • Multiplier BCD - vhdl

    Multiplier BCD - vhdl

    標簽: Multiplier vhdl BCD

    上傳時間: 2013-12-27

    上傳用戶:dongbaobao

  • complement of Multiplier

    complement of Multiplier

    標簽: complement Multiplier of

    上傳時間: 2013-12-22

    上傳用戶:helmos

  • 6x6 bit digital Multiplier

    6x6 bit digital Multiplier

    標簽: Multiplier digital 6x6 bit

    上傳時間: 2014-01-05

    上傳用戶:bruce

  • Radix 4 Booth Multiplier

    Radix 4 Booth Multiplier

    標簽: Multiplier Radix Booth

    上傳時間: 2017-09-19

    上傳用戶:zhuimenghuadie

  • A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier

    A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier

    標簽: Counterflow-Pipelined Asynchronous Multiplier Scalable

    上傳時間: 2014-01-04

    上傳用戶:jjj0202

  • 基于開關電容技術的鎖定放大器設計

    鎖定放大是微弱信號檢測的重要手段。基于相關檢測理論,利用開關電容的開關實現鎖定放大器中乘法器的功能,提出開關電容和積分器相結合以實現相關檢測的方法,并設計出一種鎖定放大器。該鎖定放大器將微弱信號轉化為與之相關的方波,通過后續電路得到正比于被測信號的直流電平,為后續采集處理提供方便。測量數據表明鎖定放大器前級可將10-6 A的電流轉換為10-1 V的電壓,后級通過帶通濾波器級聯可將信號放大1×105倍。該方法在降低噪聲的同時,可對微弱信號進行放大,線性度較高、穩定性較好。 Abstract:  Lock-in Amplifying(LIA)is one of important means for weak signal detection. Based on cross-correlation detection theory, switch in the swithched capacitor was used as Multiplier of LIA, and a new method of correlation detection was proposed combining swithched capacitor with integrator. A kind of LIA was designed which can convert the weak signal to square-wave, then DC proportional to measured signal was obtained through follow-up conditioning circuit, providing convenience for signal acquisition and processing. The measured data shows that the electric current(10-6 A) can be changed into voltage(10-1 V) by LIA, and the signal is magnified 1×105 times by cascade band-pass filter. The noise is suppressed and the weak signal is amplified. It has the advantages of good linearity and stability.

    標簽: 開關電容 鎖定放大器

    上傳時間: 2013-11-29

    上傳用戶:黑漆漆

  • AD9859芯片資料

    FEATURES400 MSPS internal clock speedIntegrated 10-bit DAC32-bit tuning wordPhase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)Excellent dynamic performance>75 dB SFDR @ 160 MHz (±100 kHz offset) AOUTSerial I/O control1.8 V power supplySoftware and hardware controlled power-down48-lead TQFP/EP packageSupport for 5 V input levels on most digital inputsPLL REFCLK Multiplier (4× to 20×)Internal oscillator; can be driven by a single crystalPhase modulation capabilityMultichip synchronization

    標簽: 9859 AD 芯片資料

    上傳時間: 2014-12-04

    上傳用戶:axin881314

  • 擴頻通信芯片STEL-2000A的FPGA實現

    針對傳統集成電路(ASIC)功能固定、升級困難等缺點,利用FPGA實現了擴頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實現NCO模塊,在下變頻模塊調用了硬核乘法器并引入CIC濾波器進行低通濾波,給出了DQPSK解調的原理和實現方法,推導出一種簡便的引入?仔/4固定相移的實現方法。采用模塊化的設計方法使用VHDL語言編寫出源程序,在Virtex-II Pro 開發板上成功實現了整個系統。測試結果表明該系統正確實現了STEL-2000A的核心功能。 Abstract:  To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core Multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.

    標簽: STEL 2000 FPGA 擴頻通信

    上傳時間: 2013-11-06

    上傳用戶:liu123

  • 擴頻通信芯片STEL-2000A的FPGA實現

    針對傳統集成電路(ASIC)功能固定、升級困難等缺點,利用FPGA實現了擴頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實現NCO模塊,在下變頻模塊調用了硬核乘法器并引入CIC濾波器進行低通濾波,給出了DQPSK解調的原理和實現方法,推導出一種簡便的引入?仔/4固定相移的實現方法。采用模塊化的設計方法使用VHDL語言編寫出源程序,在Virtex-II Pro 開發板上成功實現了整個系統。測試結果表明該系統正確實現了STEL-2000A的核心功能。 Abstract:  To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core Multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.

    標簽: STEL 2000 FPGA 擴頻通信

    上傳時間: 2013-11-19

    上傳用戶:neu_liyan

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