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UCS (Ultra Corba Simulator) is one more powerful corba client/servant simulator tool than other similar products(e.g. Telcopro s MtSim, or OpenFusion s Corba Explorer, or eaiBridge s CAST). It doesn t need idl-related helper class or IR service.
標(biāo)簽：
Simulator
simulator
powerful
servant
上傳時(shí)間：
2016-01-17
上傳用戶：hustfanenze
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You imagine? Right, there s more than one possibility, this time I ll give you tree. One for your private data, one for the common data in order to receive data from other applications like Excel, WinWord etc. and at last, I ll give you a handy-dandy class you can derive ANY MFC object from, to make it a drop target
標(biāo)簽：
possibility
imagine
Right
there
上傳時(shí)間：
2013-12-21
上傳用戶：jichenxi0730
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Abstract—In the future communication applications, users
may obtain their messages that have different importance levels
distributively from several available sources, such as distributed
storage or even devices belonging to other users. This
scenario is the best modeled by the multilevel diversity coding
systems (MDCS). To achieve perfect (information-theoretic)
secrecy against wiretap channels, this paper investigates the
fundamental limits on the secure rate region of the asymmetric
MDCS (AMDCS), which include the symmetric case as a special
case. Threshold perfect secrecy is added to the AMDCS model.
The eavesdropper may have access to any one but not more than
one subset of the channels but know nothing about the sources,
as long as the size of the subset is not above the security level.
The question of whether superposition (source separation) coding
is optimal for such an AMDCS with threshold perfect secrecy
is answered. A class of secure AMDCS (S-AMDCS) with an
arbitrary number of encoders is solved, and it is shown that linear
codes are optimal for this class of instances. However, in contrast
with the secure symmetric MDCS, superposition is shown to
be not optimal for S-AMDCS in general. In addition, necessary
conditions on the existence of a secrecy key are determined as a
design guideline.
標(biāo)簽：
Fundamental
Limits
Secure
Class
on
of
上傳時(shí)間：
2020-01-04
上傳用戶：kddlas
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游戲開發(fā)大全-game.programming.all.in.one
標(biāo)簽：
programming
game
all
one
上傳時(shí)間：
2013-06-30
上傳用戶：eeworm
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基于FPGA的單總線(ONE-WIRE)協(xié)議的實(shí)現(xiàn)源代碼.
標(biāo)簽：
ONE-WIRE
FPGA
單總線
協(xié)議
上傳時(shí)間：
2013-08-30
上傳用戶：wyc199288
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The μPSD32xx family, from ST, consists of Flash programmable system devices with a 8032 MicrocontrollerCore. Of these, the μPSD3234A and μPSD3254A are notable for having a complete implementationof the USB hardware directly on the chip, complying with the Universal Serial Bus Specification, Revision1.1.This application note describes a demonstration program that has been written for the DK3200 hardwaredemonstration kit (incorporating a μPSD3234A device). It gives the user an idea of how simple it is to workwith the device, using the HID class as a ready-made device driver for the USB connection.IN-APPLICATION-PROGRAMMING (IAP) AND IN-SYSTEM-PROGRAMMING (ISP)Since the μPSD contains two independent Flash memory arrays, the Micro Controller Unit (MCU) can executecode from one memory while erasing and programming the other. Product firmware updates in thefield can be reliably performed over any communication channel (such as CAN, Ethernet, UART, J1850)using this unique architecture. For In-Application-Programming (IAP), all code is updated through theMCU. The main advantage for the user is that the firmware can be updated remotely. The target applicationruns and takes care on its own program code and data memory.IAP is not the only method to program the firmware in μPSD devices. They can also be programmed usingIn-System-Programming (ISP). A IEEE1149.1-compliant JTAG interface is included on the μPSD. Withthis, the entire device can be rapidly programmed while soldered to the circuit board (Main Flash memory,Secondary Boot Flash memory, the PLD, and all configuration areas). This requires no MCU participation.The MCU is completely bypassed. So, the μPSD can be programmed or reprogrammed any time, anywhere, even when completely uncommitted.Both methods take place with the device in its normal hardware environment, soldered to a printed circuitboard. The IAP method cannot be used without previous use of ISP, because IAP utilizes a small amountof resident code to receive the service commands, and to perform the desired operations.
標(biāo)簽：
Demonstration
3200
USB
for
上傳時(shí)間：
2014-02-27
上傳用戶：zhangzhenyu
-
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽：
UltraScale
Xilinx
架構(gòu)
上傳時(shí)間：
2013-11-13
上傳用戶：瓦力瓦力hong
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6小時(shí)學(xué)會(huì)labview,
labview Six Hour Course – Instructor Notes
This zip file contains material designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are:
Instructor Notes.doc – this document.
labviewIntroduction-SixHour.ppt – a PowerPoint presentation containing screenshots and notes on the topics covered by the course.
Convert C to F (Ex1).vi – Exercise 1 solution VI.
Convert C to F (Ex2).vi – Exercise 2 solution subVI.
Thermometer-DAQ (Ex2).vi – Exercise 2 solution VI.
Temperature Monitor (Ex3).vi – Exercise 3 solution VI.
Thermometer (Ex4).vi – Exercise 4 solution subVI.
Convert C to F (Ex4).vi – Exercise 4 solution subVI.
Temperature Logger (Ex4).vi – Exercise 4 solution VI.
Multiplot Graph (Ex5).vi – Exercise 5 solution VI.
Square Root (Ex6).vi – Exercise 6 solution VI.
State Machine 1 (Ex7).vi – Exercise 7 solution VI.
The slides can be presented in two three hour labs, or six one hour lectures. Depending on the time and resources available in class, you can choose whether to assign the exercises as homework or to be done in class. If you decide to assign the exercises in class, it is best to assign them in order with the presentation. This way the students can create VI’s while the relevant information is still fresh. The notes associated with the exercise slide should be sufficient to guide the students to a solution. The solution files included are one possible solution, but by no means the only solution.
標(biāo)簽：
labview
上傳時(shí)間：
2013-10-13
上傳用戶：zjwangyichao
-
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽：
UltraScale
Xilinx
架構(gòu)
上傳時(shí)間：
2013-11-21
上傳用戶：wxqman
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V-BY-ONE THCV219-220 參考設(shè)計(jì)
標(biāo)簽：
V-BY-ONE
THCV
219
220
上傳時(shí)間：
2013-11-16
上傳用戶：caoyuanyuan1818
