介紹幾種cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and PERIPHERAL features, introducing the advanced register based CPU architecture i.e., the MCS 251 microcontroller architecture. The register based CPU supports a 40-byte register file. In addition, the 8xC251SA/SB/SP/SQ microcontroller has 256-Kbyte expanded external code/data memory space and 64-Kbyte stack space. The new controller is also specially designed to execute C code efficiently. More importantly, the 8xC251SA/SB/SP/SQ maintains binary code compatibility with MCS 51 microcontrollers but at the same time allows the use of the powerful MCS 251 microcontroller instruction set, with many new 8, 16 and 32 bit instructions available. The 8xC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip data RAM options and is available in 16 Kbytes and 8 Kbytes of on-chip ROM/OTPROM or ROMless options.
標(biāo)簽：
architecture
introducin
PERIPHERAL
improves
上傳時(shí)間：
2015-03-15
上傳用戶：ccclll
