為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對移相（QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計
上傳時間： 2014-01-13
上傳用戶：qoovoop
The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an external PHY through Gigabit Media IndependentInterface (GMII) and Management Data Input/Output (MDIO) interfaces and supports tri-mode(10/100/1000 Mb/s) Ethernet. Software running from the processor cache reads and writesthrough an On-Chip Memory (OCM) interface to two FIFOs that act as buffers between thedifferent clock domains of the PPC405 OCM and the TEMAC.
上傳時間： 2013-10-26
上傳用戶：yuzsu
This is the Xilinx Dual Processor Reference Designs suite. The designs illustrate a few differentdual-core architectures based on the MicroBlaze™ and PowerPC™ processors. The designsillustrate various concepts described in the Xilinx White Paper WP262 titled, “DesigningMultiprocessor Systems in Platform Studio”. There are simple software applications includedwith the reference designs that show various forms of interaction between the two processors.
標(biāo)簽： XAPP 996 雙處理器 參考設(shè)計
上傳時間： 2013-10-29
上傳用戶：旭521
在研究傳統(tǒng)家用燃?xì)鈭缶鞯幕A(chǔ)上，以ZigBee協(xié)議為平臺，構(gòu)建mesh網(wǎng)狀網(wǎng)絡(luò)實現(xiàn)網(wǎng)絡(luò)化的智能語音報警系統(tǒng)。由于傳感器本身的溫度和實際環(huán)境溫度的影響，傳感器標(biāo)定后采用軟件補償方法。為了減少系統(tǒng)費用，前端節(jié)點采用半功能節(jié)點設(shè)備，路由器和協(xié)調(diào)器采用全功能節(jié)點設(shè)備，構(gòu)建mesh網(wǎng)絡(luò)所形成的家庭內(nèi)部報警系統(tǒng)，通過通用的電話接口連接到外部的公用電話網(wǎng)絡(luò)，啟動語音模塊進行報警。實驗結(jié)果表明，在2.4 GHz頻率下傳輸，有墻等障礙物的情況下，節(jié)點的傳輸距離大約為35 m，能夠滿足家庭需要，且系統(tǒng)工作穩(wěn)定，但在功耗方面仍需進一步改善。 Abstract: On the basis of studying traditional household gas alarm system, this paper proposed the platform for the ZigBee protocol，and constructed mesh network to achieve network-based intelligent voice alarm system. Because of the sensor temperature and the actual environment temperature, this system design used software compensation after calibrating sensor. In order to reduce system cost, semi-functional node devices were used as front-end node, however, full-function devices were used as routers and coordinator，constructed alarm system within the family by building mesh network，connected to the external public telephone network through the common telephone interface, started the voice alarm module. The results indicate that nodes transmit about 35m in the distance in case of walls and other obstacles by 2.4GHz frequency transmission, this is able to meet family needs and work steadily, but still needs further improvement in power consumption.
標(biāo)簽： ZigBee 無線智能 家 報警系統(tǒng)
上傳時間： 2013-10-30
上傳用戶：swaylong
針對UHF讀寫器設(shè)計中，在符合EPC Gen2標(biāo)準(zhǔn)的情況下，對標(biāo)簽返回的高速數(shù)據(jù)進行正確解碼以達(dá)到正確讀取標(biāo)簽的要求，提出了一種新的在ARM平臺下采用邊沿捕獲統(tǒng)計定時器數(shù)判斷數(shù)據(jù)的方法，并對FM0編碼進行解碼。與傳統(tǒng)的使用定時器定時采樣高低電平的FM0解碼方法相比，該解碼方法可以減少定時器定時誤差累積的影響；可以將捕獲定時器數(shù)中斷與數(shù)據(jù)判斷解碼相對分隔開，使得中斷對解碼影響很小，實現(xiàn)捕獲與解碼的同步。通過實驗表明，這種方法提高了解碼的效率，在160 Kb/s的接收速度下，讀取一張標(biāo)簽的時間約為30次/s。 Abstract: Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator， the article introduced a new technology for FM0 decoding which counted the timer counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level， the method could reduce the accumulation of timing error and could relatively separate capture timer interrupt and the data judgment for decoding， so that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding， at 160 Kb/s receiving speed， the time of the interrogator to read a tag is about 30 times/s.
標(biāo)簽： UHF FM0 讀寫器 解碼技術(shù)
上傳時間： 2013-11-10
上傳用戶：liufei
面向Eclips的Nios II軟件構(gòu)建工具手冊 The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the Eclipse™ framework and the Eclipse C/C++ development toolkit (CDT) plugins. The Nios II SBT for Eclipse provides a consistent development platform that works for all Nios II embedded processor systems. You can accomplish all Nios II software development tasks within Eclipse, including creating, editing, building, running, debugging, and profiling programs.
上傳時間： 2013-11-02
上傳用戶：瓦力瓦力hong
一些應(yīng)用利用 Xilinx FPGA 在每次啟動時可改變配置的能力，根據(jù)所需來改變 FPGA 的功能。Xilinx Platform Flash XCFxxP PROM 的設(shè)計修訂 (Design Revisioning) 功能，允許用戶在單個PROM 中將多種配置存儲為不同的修訂版本，從而簡化了 FPGA 配置更改。在 FPGA 內(nèi)部加入少量的邏輯，用戶就能在 PROM 中存儲的多達(dá)四個不同的修訂版本之間進行動態(tài)切換。多重啟動或從多個設(shè)計修訂進行動態(tài)重新配置的能力，與 Spartan™-3E FPGA 和第三方并行 flashPROM 一起使用時所提供的 MultiBoot 選項相似。本應(yīng)用指南將進一步說明 Platform Flash PROM 如何提供附加選項來增強配置失敗時的安全性，以及如何減少引腳數(shù)量和板面積。此外，Platform Flash PROM 還為用戶提供其他優(yōu)勢：iMPACT 編程支持、單一供應(yīng)商解決方案、低成本板設(shè)計和更快速的配置加載。本應(yīng)用指南還詳細(xì)地介紹了一個包含 VHDL 源代碼的參考設(shè)計。
標(biāo)簽： Platform Flash XAPP PROM
上傳時間： 2013-10-10
上傳用戶：wangcehnglin
WP369可擴展式處理平臺-各種嵌入式系統(tǒng)的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
上傳時間： 2013-10-18
上傳用戶：cursor
本應(yīng)用指南講述一種實用的 MicroBlaze™ 系統(tǒng)，用于在非易失性 Platform Flash PROM 中存儲軟件代碼、用戶數(shù)據(jù)和配置數(shù)據(jù)，以簡化系統(tǒng)設(shè)計和降低成本。另外，本應(yīng)用指南還介紹一種可移植的硬件設(shè)計、一個軟件設(shè)計以及在實現(xiàn)流程中使用的其他腳本實用工具。 簡介許多 FPGA 設(shè)計都集成了使用 MicroBlaze 和 PowerPC™ 處理器的軟件嵌入式系統(tǒng)，這些設(shè)計同時使用外部易失性存儲器來執(zhí)行軟件代碼。使用易失性存儲器的系統(tǒng)還必須包含一個非易失性器件，用來在斷電期間存儲軟件代碼。大多數(shù) FPGA 系統(tǒng)都在電路板上使用 Platform FlashPROM (在本文中稱作 PROM)，用于在上電時加載 FPGA 配置數(shù)據(jù)。另外，許多應(yīng)用還可能使用其他非易失性器件(如 SPI Flash、Parallel Flash 或 PIC)來保存 MAC 地址等少量用戶數(shù)據(jù)，因此導(dǎo)致系統(tǒng)電路板上存在大量非易失性器件。
標(biāo)簽： MicroBlaze Platform Flash XAPP
上傳時間： 2013-10-15
上傳用戶：rocwangdp
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
標(biāo)簽： xilinx Zynq 7000 EPP
上傳時間： 2013-10-09
上傳用戶：evil
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