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  • 基于單片機AT89C51的MP3播放系統(tǒng)的設計方案

    提出一種基于單片機AT89C51SND1C的MP3播放系統(tǒng)的設計方案。單片機集成了專用的解碼器,使用K9F1208閃存作為外存儲器,放音電路采用CS4330,存儲文件通過播放器上的USB接口設備從PC機上直接下載,液晶顯示采用LCD1602。方案設計簡單,性價比高,低功耗,易擴展。由于采用的是通用單片機實現的,可以很容易地移植到其他微控制器系統(tǒng)中,有很強的市場競爭能力和實用價值。 Abstract:  A MP3 player design based on microchip AT89C51SND1C was presented, which used K9F1208 Flash chip as the memory circuit and used CS4330 as play chip. Storage files were download from PC through USB interfaces player on the device,and the LCD/602 was used as display screen. This system had characteristics of simple design,low power,easy expand,low cost and high recognition. Using of universual microchip make it easy to transplant to other microcontrol system,and have strong market competitiom and practical value.

    標簽: 89C C51 MP3 AT

    上傳時間: 2014-12-27

    上傳用戶:佳期如夢

  • PCF2116系列LCD驅動器芯片簡介及封裝庫

    1 FEATURES· Single chip LCD controller/driver· 1 or 2-line display of up to 24 characters per line, or2 or 4 lines of up to 12 characters per line· 5 ′ 7 character format plus cursor; 5 ′ 8 for kana(Japanese syllabary) and user defined symbols· On-chip:– generation of LCD supply voltage (external supplyalso possible)– generation of intermediate LCD bias voltages– oscillator requires no external components (externalclock also possible)· Display data RAM: 80 characters· Character generator ROM: 240 characters· Character generator RAM: 16 characters· 4 or 8-bit parallel bus or 2-wire I2C-bus interface· CMOS/TTL compatible· 32 row, 60 column outputs· MUX rates 1 : 32 and 1 : 16· Uses common 11 code instruction set· Logic supply voltage range, VDD - VSS: 2.5 to 6 V· Display supply voltage range, VDD - VLCD: 3.5 to 9 V· Low power consumption· I2C-bus address: 011101 SA0.

    標簽: 2116 PCF LCD 驅動器芯片

    上傳時間: 2013-11-08

    上傳用戶:laozhanshi111

  • 基于MSP430單片機和DS18B20的數字溫度計

    為了在工業(yè)生產及過程控制中準確測量溫度,設計了一種基于低功耗MSP430單片機的數字溫度計。整個系統(tǒng)通過單片機MSP430F1121A控制DS18B20讀取溫度,采用數碼管顯示,溫度傳感器DS18B20與單片機之間通過串口進行數據傳輸。MSP430系列單片機具有超低功耗,且外圍的整合性高,DS18B20只需一個端口即可實現數據通信,連接方便。通過多次實驗證明,該系統(tǒng)的測試結果與實際環(huán)境溫度一致,除了具有接口電路簡單、測量精度高、誤差小、可靠性高等特點外,其低成本、低功耗的特點使其擁有更廣闊的應用前景。 Abstract:  In order to obtain accurate measuring temperature in industrial production and process control, a digital thermometer based on MSP430 MCU is designed. The system uses MSP430F1121A MCU to control DS18B20, and gets the temperature data, which is displayed on the LED. The temperature sensor DS18B20 and MCU transmit data through serial communication. MSP430 series has ultra-low power and high integration, DS18B20 only needs one port to achieve data communication. Through many experimental results prove, this system is consistent with actual environment temperature. The system has characteristics of interface circuit simple, high measuring accuracy, minor error, high reliability, besides, the characteristics of low cost and low power make it having vaster application prospect.

    標簽: MSP 430 18B B20

    上傳時間: 2013-10-16

    上傳用戶:wettetw

  • CAT93C46 器件數據手冊

    The CAT93C46 is a 1 kb Serial EEPROM memory device which isconfigured as either 64 registers of 16 bits (ORG pin at VCC) or 128registers of 8 bits (ORG pin at GND). Each register can be written (orread) serially by using the DI (or DO) pin. The CAT93C46 features aself−timed internal write with auto−clear. On−chip Power−On Resetcircuit protects the internal logic against powering up in the wrongstate.

    標簽: CAT 93C C46 93

    上傳時間: 2013-11-20

    上傳用戶:ynzfm

  • SN65LBC170,SN75LBC170,pdf(TRIP

    The SN65LBC170 and SN75LBC170 aremonolithic integrated circuits designed forbidirectional data communication on multipointbus-transmission lines. Potential applicationsinclude serial or parallel data transmission, cabledperipheral buses with twin axial, ribbon, ortwisted-pair cabling. These devices are suitablefor FAST-20 SCSI and can transmit or receivedata pulses as short as 25 ns, with skew lessthan 3 ns.These devices combine three 3-state differentialline drivers and three differential input linereceivers, all of which operate from a single 5-Vpower supply.The driver differential outputs and the receiverdifferential inputs are connected internally to formthree differential input/output (I/O) bus ports thatare designed to offer minimum loading to the buswhenever the driver is disabled or VCC = 0. Theseports feature a wide common-mode voltage rangemaking the device suitable for party-lineapplications over long cable runs.

    標簽: 170 LBC SN TRIP

    上傳時間: 2013-10-13

    上傳用戶:ytulpx

  • AD9859芯片資料

    FEATURES400 MSPS internal clock speedIntegrated 10-bit DAC32-bit tuning wordPhase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)Excellent dynamic performance>75 dB SFDR @ 160 MHz (±100 kHz offset) AOUTSerial I/O control1.8 V power supplySoftware and hardware controlled power-down48-lead TQFP/EP packageSupport for 5 V input levels on most digital inputsPLL REFCLK multiplier (4× to 20×)Internal oscillator; can be driven by a single crystalPhase modulation capabilityMultichip synchronization

    標簽: 9859 AD 芯片資料

    上傳時間: 2014-12-04

    上傳用戶:axin881314

  • FET430PIF自制資料

    The MSP-FET430PIF is a Parallel Port interface (does not include target board) that is used to program and debug MSP430 FET tools and test boards through the JTAG interface. This interface is included in our FET tools, but sold without the development board. This interface uses a Parallel PC Port to communicate to the Debugger Software (IAR Kickstart software included) running on the PC. The interface uses the standard 14 pin header to communicate to the MSP430 device using the standard JTAG protocol. The flash memory can be erased and programmed in seconds with only a few keystrokes, and since the MSP430 flash is extremely low power, no external power supply is required. The tool has an integrated software environment and connects directly to the PC which greatly simplifies the set-up and use of the tool. The flash development tool supports development with all MSP430 flash parts. Features MSP430 debugging interface to connect a MSP430-Flash-device to a Parallel port on a PC Supports JTAG debug protocol (NO support for Spy-Bi-Wire (2-wire JTAG) debug protocol, Spy-Bi-Wire (2-wire JTAG) is supported by MSP-FET430UIF) Parallel Port cable and a 14-conductor target cable Full documentation on CD ROM Integrated IAR Kickstart user interface which includes: Assembler Linker Limulator Source-level debugger Limited C-compiler Technical specifications: Backwardly compatable with existing FET tool boards.

    標簽: FET 430 PIF

    上傳時間: 2013-10-26

    上傳用戶:fengweihao158@163.com

  • MSP430 USB JTAG自制資料

    The MSP-FET430U14 is a powerful flash emulation tool to quickly begin application development on the MSP430 MCU. It includes USB debugging interface used to program and debug the MSP430 in-system through the JTAG interface or the pin saving Spy Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased and programmed in seconds with only a few keystrokes, and since the MSP430 flash is ultra-low power, no external power supply is required. The debugging tool interfaces the MSP430 to the included integrated software environment and includes code to start your design immediately.  The MSP-FET430UIF development tools supports development with all MSP430 flash devices

    標簽: JTAG MSP 430 USB

    上傳時間: 2013-10-28

    上傳用戶:13691535575

  • 看門狗電路的分析

    根據看門狗電路的原理,設計出簡單適用、性能可靠的1TrL型看門狗電路以及價格低廉、性能可靠的微功耗CMOS型看門狗電路,同時還介紹了常用的uP監(jiān)視器O型看門狗電路。關鍵詞:看門狗電路;1TrL型;CMOS型Abstract:In accordance with the principle of WDT (Watch Dog Timer 1circuit,design a,IT.L type WTD circuit,it is a dimple an d applicable an d reliable on performanceo Design a CMOS type WTD circuit,it is low prices and mini-power consumption。Also the article describes a common uP type WTD circuit。Key word:WDT circuit;TFL type;CMOS typ e

    標簽: 看門狗電路

    上傳時間: 2013-11-05

    上傳用戶:685

  • Virtex-5, Spartan-DSP FPGAs Ap

    Virtex-5, Spartan-DSP FPGAs Application Note This application note demonstrates how efficient implementations of Digital Up Converters(DUC) and Digital Down Converters (DDC) can be done by leveraging the Xilinx DSP IPportfolio for increased productivity and reduced time to development. Step-by-step instruction is given on how to perform system-level trade off analysis and develop the most efficient FPGA implementation, thus allowing engineers a flexible, low-cost and low-power alternative to ASSP technologies.

    標簽: Spartan-DSP Virtex FPGAs Ap

    上傳時間: 2013-10-23

    上傳用戶:raron1989

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