The C8051F020/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins (C8051F020/2) or 32 digital I/O pins (C8051F021/3). Highlighted features are listed below; refer to Table 1.1 for specific product feature selection.
標(biāo)簽： C8051F020 數(shù)據(jù)手冊(cè)
上傳時(shí)間： 2013-11-08
上傳用戶：lwq11
STM8S105xx_中文資料：這本數(shù)據(jù)手冊(cè)描述了STM8S105xx基礎(chǔ)型系列單片機(jī)的特點(diǎn)、引腳分配、電氣特性、機(jī)械特性和訂購(gòu)信息。 如果需要關(guān)于STM8S單片機(jī)存儲(chǔ)器、寄存器和外設(shè)等的詳細(xì)信息，請(qǐng)參考STM8S系列單片機(jī)參考手冊(cè)(RM0016) 。 如果需要關(guān)于內(nèi)部Flash存儲(chǔ)器的編程、擦除和保護(hù)的信息，請(qǐng)參考STM8S閃存編程手冊(cè)(PM0051) 。 如果需要關(guān)于調(diào)試和SWIM(single wire interface module單線接口模塊)，請(qǐng)參考STM8SWIM 通信協(xié)議和調(diào)試模塊用戶手冊(cè)(UM0470) 。 如果需要關(guān)于STM8 內(nèi)核的信息，請(qǐng)參考STM8 CPU編程手冊(cè)(PM0044) 。
上傳時(shí)間： 2013-11-03
上傳用戶：JasonC
The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
上傳時(shí)間： 2013-10-24
上傳用戶：s藍(lán)莓汁
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上傳時(shí)間： 2013-11-07
上傳用戶：swing
Keil C51 V8 專業(yè)開發(fā)工具（PK51） PK51是為8051系列單片機(jī)所設(shè)計(jì)的開發(fā)工具，支持所有8051系列衍生產(chǎn)品，，支持帶擴(kuò)展存儲(chǔ)器和擴(kuò)展指令集（例如Dallas390/5240/400,Philips 51MX,Analog Devices MicroConverters）的新設(shè)備,以及支持很多公司的一流的設(shè)備和IP內(nèi)核,比如Analog Devices, Atmel, Cypress Semiconductor, Dallas Semiconductor, Goal, Hynix, Infineon, Intel, NXP(founded by Philips), OKI, Silicon Labs,SMSC, STMicroeleectronics,Synopsis, TDK, Temic, Texas Instruments,Winbond等。 通過PK51專業(yè)級(jí)開發(fā)工具，可以輕松地了解8051的On-chip peripherals與及其它關(guān)鍵特性。 The PK51專業(yè)級(jí)開發(fā)工具包括… l μVision Ø 集成開發(fā)環(huán)境 Ø 調(diào)試器 Ø 軟件模擬器 l Keil 8051擴(kuò)展編譯工具 Ø AX51宏匯編程序 Ø ANSI C編譯工具 Ø LX51 連接器 Ø OHX51 Object-HEX 轉(zhuǎn)換器 l Keil 8051編譯工具 Ø A51宏匯編程序 Ø C51 ANSI C編譯工具 Ø BL51 代碼庫(kù)連接器 Ø OHX51 Object-HEX 轉(zhuǎn)換器 Ø OC51 集合目標(biāo)轉(zhuǎn)換器 l 目標(biāo)調(diào)試器 Ø FlashMON51 目標(biāo)監(jiān)控器 Ø MON51目標(biāo)監(jiān)控器 Ø MON390 (Dallas 390)目標(biāo)監(jiān)控器 Ø MONADI (Analog Devices 812)目標(biāo)監(jiān)控器 Ø ISD51 在系統(tǒng)調(diào)試 l RTX51微實(shí)時(shí)內(nèi)核 你應(yīng)該考慮PK51開發(fā)工具包,如果你… l 需要用8051系列單片機(jī)來開發(fā) l 需要開發(fā) Dallas 390 或者 Philips 51MX代碼 l 需要用C編寫代碼 l 需要一個(gè)軟件模擬器或是沒有硬件仿真器 l 需要在單芯片上基于小實(shí)時(shí)內(nèi)核創(chuàng)建復(fù)雜的應(yīng)用
上傳時(shí)間： 2013-10-30
上傳用戶：yy_cn
LVDS、xECL、CML（低電壓差分信號(hào)傳輸、發(fā)射級(jí)耦合邏輯、電流模式邏輯）………4多點(diǎn)式低電壓差分信號(hào)傳輸(M-LVDS) ……………………………………………………8數(shù)字隔離器 ………………………………………………………………………………10RS-485/422 …………………………………………………………………………………11RS-232………………………………………………………………………………………13UART（通用異步收發(fā)機(jī)）…………………………………………………………………16CAN（控制器局域網(wǎng)）……………………………………………………………………18FlatLinkTM 3G ………………………………………………………………………………19SerDes（串行G 比特收發(fā)機(jī)及LVDS）……………………………………………………20DVI（數(shù)字視頻接口）/PanelBusTM ………………………………………………………22TMDS（最小化傳輸差分信號(hào)） …………………………………………………………24USB 集線器控制器及外設(shè)器件 …………………………………………………………25USB 接口保護(hù) ……………………………………………………………………………26USB 電源管理 ……………………………………………………………………………27PCI Express® ………………………………………………………………………………29PCI 橋接器 …………………………………………………………………………………33卡總線 (CardBus) 電源開關(guān) ………………………………………………………………341394 (FireWire®, 火線®) ……………………………………………………………………36GTLP (Gunning Transceiver Logic Plus，體效應(yīng)收發(fā)機(jī)邏輯+) ………………………………39VME（Versa Module Eurocard）總線 ………………………………………………………41時(shí)鐘分配電路 ……………………………………………………………………………42交叉參考指南 ……………………………………………………………………………43器件索引 …………………………………………………………………………………47技術(shù)支持 …………………………………………………………………………………48 德州儀器（TI）為您提供了完備的接口解決方案，使得您的產(chǎn)品別具一格，并加速了產(chǎn)品面市。憑借著在高速、復(fù)合信號(hào)電路、系統(tǒng)級(jí)芯片 (system-on-a-chip ) 集成以及先進(jìn)的產(chǎn)品開發(fā)工藝方面的技術(shù)專長(zhǎng)，我們將能為您提供硅芯片、支持工具、軟件和技術(shù)文檔，使您能夠按時(shí)的完成并將最佳的產(chǎn)品推向市場(chǎng)，同時(shí)占據(jù)一個(gè)具有競(jìng)爭(zhēng)力的價(jià)格。本選擇指南為您提供與下列器件系列有關(guān)的設(shè)計(jì)考慮因素、技術(shù)概述、產(chǎn)品組合圖示、參數(shù)表以及資源信息：
上傳時(shí)間： 2013-10-21
上傳用戶：Jerry_Chow
We offer a broad line of high performance low dropout (LDO) linear regulators with fasttransient response, excellent line and load regulation, and very wide input voltage rangefrom 0.9V to 100V. Output currents range from 20mA to 10A, with positive, negative andmultiple output versions available. Many devices offer output voltage operation <0.8V andsome feature operation as low as 0V, even with a single supply. Most are stable with ceramicoutput capacitors. LDO regulators can be applied in virtually any application.
上傳時(shí)間： 2013-11-15
上傳用戶：努力努力再努力
介紹了SoPC（System on a Programmable Chip）系統(tǒng)的概念和特點(diǎn)，給出了基于PLB總線的異步串行通信（UART）IP核的硬件設(shè)計(jì)和實(shí)現(xiàn)。通過將設(shè)計(jì)好的UART IP核集成到SoPC系統(tǒng)中加以驗(yàn)證，證明了所設(shè)計(jì)的UART IP核可以正常工作。該設(shè)計(jì)方案為其他基于SoPC系統(tǒng)IP核的開發(fā)提供了一定的參考。
上傳時(shí)間： 2013-11-12
上傳用戶：894448095
Single-Ended and Differential S-Parameters Differential circuits have been important incommunication systems for many years. In the past,differential communication circuits operated at lowfrequencies, where they could be designed andanalyzed using lumped-element models andtechniques. With the frequency of operationincreasing beyond 1GHz, and above 1Gbps fordigital communications, this lumped-elementapproach is no longer valid, because the physicalsize of the circuit approaches the size of awavelength.Distributed models and analysis techniques are nowused instead of lumped-element techniques.Scattering parameters, or S-parameters, have beendeveloped for this purpose [1]. These S-parametersare defined for single-ended networks. S-parameterscan be used to describe differential networks, but astrict definition was not developed until Bockelmanand others addressed this issue [2]. Bockelman’swork also included a study on how to adapt single-ended S-parameters for use with differential circuits[2]. This adaptation, called “mixed-mode S-parameters,” addresses differential and common-mode operation, as well as the conversion betweenthe two modes of operation.This application note will explain the use of single-ended and mixed-mode S-parameters, and the basicconcepts of microwave measurement calibration.
上傳時(shí)間： 2014-03-25
上傳用戶：yyyyyyyyyy
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
標(biāo)簽： Cortex-M 1850 LPC 內(nèi)核微控制器
上傳時(shí)間： 2014-12-31
上傳用戶：zhuoying119
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