《單片機與嵌入式系統應用》論文--嵌入式GSM短信息接口的軟硬件設計，文章給出一個小型的嵌入式SMS中/英文短信信息接口的設計，并詳細討論PDU模式的短信息格式和中文短信息軟件解碼的設計。
上傳時間： 2013-07-12
上傳用戶：lanwei
·詳細說明：雙音多頻（DTMF）信號發生器的使用源程序，vc 編寫，與《雙音多頻（DTMF）接收器的使用源程序》聯合用- The double sound multi- frequencies (DTMF) the signal generating device use source program, the vc compilation, (DTMF) Receiver Use Source p
上傳時間： 2013-07-23
上傳用戶：tianjinfan
SIM900A采用工業標準接口，工作頻率為GSM/GPRS 850/900/1800/1900MHz，可以低功耗實現語音、SMS、數據和傳真信息的傳輸。
上傳時間： 2013-05-19
上傳用戶：龍飛艇
Abstract: The MAX3108 is a complete high-performance universal asynchronous receiver-transmitter (UART) in a tiny 2.1mm ×
標簽： Programming Rates Baud 3108
上傳時間： 2014-12-23
上傳用戶：清風冷雨
The LT®6552 is a specialized dual-differencing 75MHzoperational amplifier ideal for rejecting common modenoise as a video line receiver. The input pairs are designedto operate with equal but opposite large-signal differencesand provide exceptional high frequency commonmode rejection (CMRR of 65dB at 10MHz), therebyforming an extremely versatile gain block structure thatminimizes component count in most situations. The dualinput pairs are free to take on independent common modelevels, while the two voltage differentials are summedinternally to form a net input signal.
上傳時間： 2014-12-23
上傳用戶：13691535575
Designers of signal receiver systems often need to performcascaded chain analysis of system performancefrom the antenna all the way to the ADC. Noise is a criticalparameter in the chain analysis because it limits theoverall sensitivity of the receiver. An application’s noiserequirement has a signifi cant infl uence on the systemtopology, since the choice of topology strives to optimizethe overall signal-to-noise ratio, dynamic range andseveral other parameters. One problem in noise calculationsis translating between the various units used by thecomponents in the chain: namely the RF, IF/baseband,and digital (ADC) sections of the circuit.
上傳時間： 2014-12-05
上傳用戶：cylnpy
Avalanche photo diode (APD) receiver modules arewidely used in fi ber optic communication systems. AnAPD module contains the APD and a signal conditioningamplifi er, but is not completely self contained. It stillrequires signifi cant support circuitry including a highvoltage, low noise power supply and a precision currentmonitor to indicate the signal strength. The challenge issqueezing this support circuitry into applications withlimited board space. The LT®3482 addresses this challengeby integrating a monolithic DC/DC step-up converter andan accurate current monitor. The LT3482 can supportup to a 90V APD bias voltage, and the current monitorprovides better than 10% accuracy over four decades ofdynamic range (250nA to 2.5mA).
上傳時間： 2014-01-18
上傳用戶：wenyuoo
介紹一種基于C8051F060單片機和NAND Flash的數據采集存儲系統，該系統可實現3路信號采樣，每路采樣率為5KS/s,通過異步串行通信接口實現數據傳輸。并詳細說明系統的軟件設計。 Abstract: An acquisition and storage system based on C8051F060and NAND Flash is designed in this paper.The system is used to sample three-channel of signal,5KSPS each channel,and can upload data to test bench through UART（Universal Asynchronous Receiver/Transmitter）.The software design is discussed in detail.
上傳時間： 2013-10-12
上傳用戶：Jesse_嘉偉
在嵌入式系統中，嵌入式CPU往往要通過各種串行數據總線與“外界”進行通信。在應用中，異步的串行數據通信用得較多，而通用異步收發器UART（Universal Asynchronous Receiver Transmitter）在其中扮演著重要角色：完成數據的串并轉換，即把并行數據按照通信波特率轉化為通信協議中規定的串行數據流，也可從串行數據流中取出有用數據轉變為并行數據。而UART與CPU接口簡單，CPU只需通過執行讀寫操作即可完成收發數據，從而完成與外界的通信。有許多現成的芯片可以實現UART的功能，如常用的Intel8250/8251接口芯片就可以作為RS232、RS422串口的UART控制芯片。
上傳時間： 2013-11-25
上傳用戶：www240697738
The SN65LBC170 and SN75LBC170 aremonolithic integrated circuits designed forbidirectional data communication on multipointbus-transmission lines. Potential applicationsinclude serial or parallel data transmission, cabledperipheral buses with twin axial, ribbon, ortwisted-pair cabling. These devices are suitablefor FAST-20 SCSI and can transmit or receivedata pulses as short as 25 ns, with skew lessthan 3 ns.These devices combine three 3-state differentialline drivers and three differential input linereceivers, all of which operate from a single 5-Vpower supply.The driver differential outputs and the receiverdifferential inputs are connected internally to formthree differential input/output (I/O) bus ports thatare designed to offer minimum loading to the buswhenever the driver is disabled or VCC = 0. Theseports feature a wide common-mode voltage rangemaking the device suitable for party-lineapplications over long cable runs.
上傳時間： 2013-10-13
上傳用戶：ytulpx
