This paper presents several low-latency mixed-timing FIFO (first-in–first-out) interfaces designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The designs are then adapted to work between systems with very long interconnect delays, by migrating a single-clock solution by Carloni et al. (1999, 2000, and 2001) (for “l(fā)atency-insensitive” protocols) to mixed-timing domains. The new designs can be made arbitrarily robust with regard to metastability and interface operating speeds. Initial simulations for both latency and throughput are promising.
標(biāo)簽： mixed-timing low-latency interfaces first-out
上傳時(shí)間： 2015-10-08
上傳用戶：dapangxie
This file (the project file) contains information at the project level and is used to build a single project or subproject. Other users can share the project (.dsp) file, but they should export the makefiles locally.
標(biāo)簽： project file information the
上傳時(shí)間： 2013-12-07
上傳用戶：hj_18
安全移除usb設(shè)備功能，可禁止某類usb設(shè)備的使用，實(shí)行系統(tǒng)安全控制Removing a USB drive using the Windows tray icon is easy - especially if you single left-click it... But sometimes it s useful to it from your program
上傳時(shí)間： 2015-10-15
上傳用戶：dianxin61
Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
標(biāo)簽： representation Magnitude the magnitude
上傳時(shí)間： 2013-12-24
上傳用戶：金宜
A system simulation environment in Matlab/Simulink of RFID is constructed in this paper. Special attention is emphasized on the analog/RF circuit.Negative effects are concerned in the system model,such as phase noise of the local oscillator,TX-RX coupling,reflection of the environment, AWGN noise,DC offset,I/Q mismatch,etc.Performance of the whole system can be evaluated by changing the coding method,parameters of building blocks,and operation distance.Finally,some simulation results are presented in this paper.
標(biāo)簽： environment constructed simulation Simulink
上傳時(shí)間： 2014-01-09
上傳用戶：zhangliming420
The MAX504/MAX515 are low-power, voltage-output, 10-bit digital-to-analog converters (DACs) specified for single +5V power-supply operation.用于DA轉(zhuǎn)換芯片選型
標(biāo)簽： digital-to-analog voltage-output converters MAX
上傳時(shí)間： 2015-11-26
上傳用戶：541657925
/// ////單端輸入，定時(shí)啟動，由T2定時(shí)，選擇AIN0.3為ADC0轉(zhuǎn)化通道//////////////// //////single.c/////////////////////////////////// #include "lcd.h"http://筆者所寫的LCD顯示頭文件，具體見LCD章節(jié) /*若讀者沒有條件使用"lcd.h"的各顯示和鍵盤函數(shù),則可在lcd.h文件中如下定義:
上傳時(shí)間： 2015-11-26
上傳用戶：vodssv
TI 公司 三相交流電機(jī)矢量控制源程序，F(xiàn)24x ACI3_3 3-Phase Sensored Field Oriented Control (FOC)
上傳時(shí)間： 2013-12-20
上傳用戶：縹緲
Make and answer phone calls Detect tone and pulse digit from the phone line Capture Caller ID Support blind transfer, single-step transfer/conference, consultation transfer/conference, hold, unhold. Control of the local phone handset, microphone and speaker of the modem Send and receive faxes Play and record on the phone line or sound card Play music in background mode Silence detection VU Meter Wave sound editor that allows your end-users to edit their own sound files. Voice recognition and voice synthesis. Full control over the serial port device ZModem file transfer utility File compression and encryption utility
標(biāo)簽： phone and Capture Detect
上傳時(shí)間： 2013-11-30
上傳用戶：水中浮云
An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
標(biāo)簽： interconnections approach general include
上傳時(shí)間： 2015-12-12
上傳用戶：lyy1234
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