摘 要 瞬態(tài)仿真領(lǐng)域的許多工作需要獲得可視化數(shù)據(jù), 仿真電路不能將輸出參數(shù)繪制成圖形時研究工作將受到很大影響. 而權(quán)威電路仿真軟件PSpice 在這個方面不盡如人意. 本文提出了一種有效的解決辦法: 通過MATLAB 編程搭建一個PSpice 與MATLAB 的數(shù)據(jù)接口,使PSpice輸出數(shù)據(jù)文件可以導(dǎo)入到MATLAB中繪制圖形. 這令我們能夠很方便地獲得數(shù)據(jù)的規(guī)律以有效地分析仿真結(jié)果, 這項技術(shù)對于教學(xué)和工程實踐都有比較實際的幫助.關(guān)鍵詞: 瞬態(tài)仿真 仿真程序 PSpice MATLAB 可視化數(shù)據(jù)The Data Transfer from Pspice to MATLABWu hao Ning yuanzhong Liang yingAbstract Many works in the area of transient simulation has shown how a emulator such asPSpice can be interfaced to an control analysis package such as MATLAB to get viewdata. Thepaper describes how such interfaces can be made using the MATLAB programming. The platformas a typical platform will solve the problem that PSpice software sometimes can not draw the datato a picture. It can make us find the rule from numerous data very expediently, so we can analyzethe outcome of the simulation. And it also can be used in the field of education.Keywords Transient Simulation Emulator PSpice MATLAB Viewdata1 引言科學(xué)研究和工程應(yīng)用常需要進行電路仿真 PSpice可進行直流 交流 瞬態(tài)等基本電路特性分析 也可進行蒙托卡諾 MC 統(tǒng)計分析 最壞情況 Wcase 分析 優(yōu)化設(shè)計等復(fù)雜電路特性分析 它是國際上仿真電路的權(quán)威軟件 而MATLAB的主要特點有 高效方便的矩陣和數(shù)組運算 編程效率高 結(jié)構(gòu)化面向?qū)ο?方便的繪圖功能 用戶使用方便 工具箱功能強大 兩者各有著重點 兩種軟件結(jié)合應(yīng)用 對研究工作有很重要的意義香港理工大學(xué)Y. S. LEE 等人首先將PSpice和MATLAB結(jié)合 開發(fā)了電力電子電路優(yōu)化用的CAD 程序MATSPICE[6] 將兩者相結(jié)合的關(guān)鍵在于 如何用MATLAB 獲取PSpice的仿真數(shù)據(jù) 對此參考文獻 6 里沒有詳細敘述 本文著重說明用MATLAB 讀取PSpice仿真數(shù)據(jù)的具體方法本論文利用MATLAB對PSpice仿真出的數(shù)據(jù)處理繪制出后者無法得到或是效果不好的仿真圖形 下面就兩者結(jié)合使用的例子 進行具體說明
標(biāo)簽： MATLAB PSpice 數(shù)據(jù) 接口技術(shù)
上傳時間： 2013-10-20
上傳用戶：wuchunzhong
This application note explains the XC9500™/XL/XV Boundary Scan interface anddemonstrates the software available for programming and testing XC9500/XL/XV CPLDs. Anappendix summarizes the iMPACT software operations and provides an overview of theadditional operations supported by XC9500/XL/XV CPLDs for in-system programming.
上傳時間： 2013-11-15
上傳用戶：fengweihao158@163.com
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上傳時間： 2013-11-11
上傳用戶：zhouli
This application note contains a reference design consisting of HDL IP and Xilinx AdvancedConfiguration Environment (ACE) software utilities that give designers great flexibility increating in-system programming (ISP) solutions. In-system programming support allowsdesigners to revise existing designs, package the new bitstream programming files with theprovided software utilities, and update the remote system through the JTAG interface using theEmbedded JTAG ACE Player.
上傳時間： 2013-11-14
上傳用戶：JIMMYCB001
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
標(biāo)簽： Spartan-XL Express XAPP FPGA
上傳時間： 2014-12-28
上傳用戶：hewenzhi
WP369可擴展式處理平臺-各種嵌入式系統(tǒng)的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
上傳時間： 2013-10-22
上傳用戶：685
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
標(biāo)簽： xilinx Zynq 7000 EPP
上傳時間： 2013-11-01
上傳用戶：dingdingcandy
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對移相（QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達到了預(yù)期的設(shè)計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計
上傳時間： 2014-01-13
上傳用戶：qoovoop
波長信號的解調(diào)是實現(xiàn)光纖光柵傳感網(wǎng)絡(luò)的關(guān)鍵，基于現(xiàn)有的光纖光柵傳感器解調(diào)方法，提出一種基于FPGA的雙匹配光纖光柵解調(diào)方法，此系統(tǒng)是一種高速率、高精度、低成本的解調(diào)系統(tǒng)，并且通過引入雙匹配光柵有效地克服了雙值問題同時擴大了檢測范圍。分析了光纖光柵的測溫原理并給出了該方案軟硬件設(shè)計，綜合考慮系統(tǒng)的解調(diào)精度和FPGA的處理速度給出了基于拉格朗日的曲線擬合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
標(biāo)簽： FPGA 光纖光柵 解調(diào)系統(tǒng)
上傳時間： 2014-07-24
上傳用戶：caiguoqing
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標(biāo)簽： Transceiver Virtex Wizar GTP
上傳時間： 2013-10-23
上傳用戶：leyesome
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