EWB軟件是交互圖像技術(shù)有限公司(INTERACTIVE IMAGE Technologies Ltd)在九十年代初推出的EDA軟件
上傳時(shí)間： 2013-05-26
上傳用戶(hù)：heart_2007
Abstract: A digital RF modulator, an integrated solution that satisfies stringent DOCSIS RF-performancerequirements, takes advantage of modern Technologies like high-performance wideband digital-to-analogconversion and CMOS technology scaling. This application note describes the concept and advantages ofa digital quadrature amplitude modulation (QAM) modulator that uses the direct-RF architecture to enablea cable access platform (CCAP) system.
標(biāo)簽： 集成 數(shù)字RF 調(diào)制器 方案
上傳時(shí)間： 2013-10-20
上傳用戶(hù)：drink！
Abstract: What can be simpler than designing with CMOS and BiCMOS? These Technologies are very easy to use butthey still require careful design. This tutorial discusses the odd case of circuits that seem to work but exhibit somepeculiar behaviors—including burning the designer's fingers!
上傳時(shí)間： 2013-11-03
上傳用戶(hù)：dick_sh
由lnfineon Technologies (IT)公司推出的COOLMOS ICE2A165／2,65／365系列芯片是PWM+MOSFET二合一芯片，其優(yōu)點(diǎn)是：用它做開(kāi)關(guān)電源，無(wú)需加散熱器，在通用電網(wǎng)即可輸出20～50W 的功率；保護(hù)功能齊全；電路結(jié)構(gòu)簡(jiǎn)單；能自動(dòng)降低空載時(shí)的工作頻率，從而降低待機(jī)狀態(tài)的損耗，故在中小功率開(kāi)關(guān)電源中有著廣泛的應(yīng)用前景。
標(biāo)簽： COOLMOS ICE 應(yīng)用研究
上傳時(shí)間： 2013-11-09
上傳用戶(hù)：chenjjer
This application note is an overview discussion of theLinear Technology SPICE macromodel library. It assumeslittle if any prior knowledge of this software library or itshistory. However, it does assume familiarity with both theanalog simulation program SPICE (or one of its manyderivatives), and modern day op amps, including bipolar,JFET, and MOSFET amplifier Technologies
標(biāo)簽： LTC 運(yùn)算放大器 模型
上傳時(shí)間： 2013-11-14
上傳用戶(hù)：zhanditian
COOLMOS ICE2A165/265/365是Infineon Technologies 公司推出的系列PWM+MOSFET二合一芯片，其突出特點(diǎn)是由其組成的開(kāi)關(guān)電源，在市電電網(wǎng)中工作時(shí)，無(wú)需外加散熱器即可輸出20～50W的輸出功率;且能自動(dòng)降低空載時(shí)的工作頻率，從而降低待機(jī)狀態(tài)的損耗;同時(shí)還具有過(guò)、欠壓保護(hù)、過(guò)熱保護(hù)、過(guò)流保護(hù)以及自恢復(fù)功能，因而在中小功率開(kāi)關(guān)電源中有著廣泛 的應(yīng)用前景
標(biāo)簽： COOLMOS 組合式 器件 中的應(yīng)用
上傳時(shí)間： 2013-10-17
上傳用戶(hù)：HGH77P99
以C8051F020為核心處理器，設(shè)計(jì)無(wú)線(xiàn)傳感器網(wǎng)絡(luò)數(shù)據(jù)采集系統(tǒng)。系統(tǒng)采用SZ05-ADV型無(wú)線(xiàn)通訊模塊組建Zigbee無(wú)線(xiàn)網(wǎng)絡(luò)，結(jié)合嵌入式系統(tǒng)的軟硬件技術(shù)，完成終端節(jié)點(diǎn)的8路傳感器信號(hào)的數(shù)據(jù)采集。現(xiàn)場(chǎng)8路信號(hào)通過(guò)前端處理后，分別送入C8051F020的12位A/D轉(zhuǎn)換器進(jìn)行轉(zhuǎn)換。經(jīng)過(guò)精確處理、存儲(chǔ)后的現(xiàn)場(chǎng)數(shù)據(jù)，通過(guò)Zigbee無(wú)線(xiàn)網(wǎng)絡(luò)傳送到上位機(jī)，系統(tǒng)可達(dá)到汽車(chē)試驗(yàn)中無(wú)線(xiàn)測(cè)試的目的。 Abstract: This paper designs a wireless sensor network system for data acquisition with C8051F020 as core processors.The system used SZ05-ADV wireless communication module，set up a Zigbee wireless network， combined with hardware and software Technologies of embedded systems，completed the end-node 8-locale sensor signal data acquisition.Eight locale signals were sent separately into the 12-bit ADC of C8051F020 for conversion through front treatment.After accurate processing and storage，the locale data was transmitted to the host computer through Zigbee wireless.The system achieves the purpose of wireless testing in vehicle trial.
標(biāo)簽： C8051F020 Zigbee 汽車(chē)測(cè)試 系統(tǒng)設(shè)計(jì)
上傳時(shí)間： 2013-11-23
上傳用戶(hù)：dsgkjgkjg
Virtex-5, Spartan-DSP FPGAs Application Note This application note demonstrates how efficient implementations of Digital Up Converters(DUC) and Digital Down Converters (DDC) can be done by leveraging the Xilinx DSP IPportfolio for increased productivity and reduced time to development. Step-by-step instruction is given on how to perform system-level trade off analysis and develop the most efficient FPGA implementation, thus allowing engineers a flexible, low-cost and low-power alternative to ASSP Technologies.
標(biāo)簽： Spartan-DSP Virtex FPGAs Ap
上傳時(shí)間： 2013-10-23
上傳用戶(hù)：raron1989
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET Technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶(hù)：瓦力瓦力hong
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon Technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時(shí)間： 2013-10-22
上傳用戶(hù)：ztj182002
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