演示linux下面top命令的源代碼,top是用來查看系統CPU及資源占用比的.
上傳時間： 2013-12-16
上傳用戶：ztj182002
這是從網上down的關于vc的自學書籍希望對大家能有幫助 獨樂樂 不如大家樂
上傳時間： 2013-12-21
上傳用戶：kelimu
Joey is j2me client server application for for mobile platform. Build on top j2mepolish
標簽： application j2mepolish for platform
上傳時間： 2016-09-29
上傳用戶：sz_hjbf
Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1
標簽： Compensation Conversion Designing MegaCore
上傳時間： 2016-10-07
上傳用戶：wendy15
3D Statistical shape analysis by SHPARM method: code and paper. From the top group at UNC.
標簽： Statistical analysis SHPARM method
上傳時間： 2016-10-20
上傳用戶：wfl_yy
iic總線控制器VHDL實現 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist
標簽： VHDL c_control vhd control
上傳時間： 2016-10-30
上傳用戶：woshiayin
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上傳時間： 2013-12-13
上傳用戶：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上傳時間： 2014-01-20
上傳用戶：三人用菜
網上down的一個電機控制的，據說很吧u錯啊，有興趣可以看下啊。
上傳時間： 2016-11-08
上傳用戶：13188549192
黑客防線下載系統(http://www.hacker.com.cn/down) 感謝使用本軟件，有任何疑問請訪問黑客防線官方網站（http://www.hacker.com.cn）并提出。我們將盡快為您解決。 更多精品黑客工具請訪問：www.hacker.com.cn/vip
上傳時間： 2014-06-09
上傳用戶：cx111111
