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  • 無線電能傳輸技術展望 黃學良

      無線電能傳輸技術(Wireless Power Transfer Technology)又稱無接觸電能傳輸(Contactless Power Transmission,CPT)技術早在1890 年,由著名電氣工程師(物理學家)尼古拉·特斯拉(Nikola Tesla) 提出。  

    標簽: 無線 傳輸技術 電能

    上傳時間: 2013-10-20

    上傳用戶:zhliu007

  • SWIFT設計軟件工具

    SWIFT 提供的服務   1、接入服務   SWIFT的接入服務通過SWIFTAlliance的系列產(chǎn)品完成,包括:   (1) SWIFTAlliance Access and Entry:傳送FIN信息的接口軟件;   (2) SWIFTAlliance Gateway:接入SWIFTNet的窗口軟件;   (3) SWIFTAlliance Webstation:接入SWIFTNet的桌面接入軟件;   (4) File Transfer Interface:文件傳輸接口軟件,通過SWIFTNet FileAct是用戶方便的訪問其后臺辦公系統(tǒng)。   SWIFTNET Link軟件內嵌在SWIFTAlliance Gateway和SWIFTAlliance Webstation中,提供傳輸、標準化、安全和管理服務。連接后,它確保用戶可以用同一窗口多次訪問SWIFTNet,獲得不同服務。

    標簽: SWIFT 設計軟件

    上傳時間: 2014-12-03

    上傳用戶:huyiming139

  • Verilog_HDL的基本語法詳解(夏宇聞版)

            Verilog_HDL的基本語法詳解(夏宇聞版):Verilog HDL是一種用于數(shù)字邏輯電路設計的語言。用Verilog HDL描述的電路設計就是該電路的Verilog HDL模型。Verilog HDL既是一種行為描述的語言也是一種結構描述的語言。這也就是說,既可以用電路的功能描述也可以用元器件和它們之間的連接來建立所設計電路的Verilog HDL模型。Verilog模型可以是實際電路的不同級別的抽象。這些抽象的級別和它們對應的模型類型共有以下五種:   系統(tǒng)級(system):用高級語言結構實現(xiàn)設計模塊的外部性能的模型。   算法級(algorithm):用高級語言結構實現(xiàn)設計算法的模型。   RTL級(Register Transfer Level):描述數(shù)據(jù)在寄存器之間流動和如何處理這些數(shù)據(jù)的模型。   門級(gate-level):描述邏輯門以及邏輯門之間的連接的模型。   開關級(switch-level):描述器件中三極管和儲存節(jié)點以及它們之間連接的模型。   一個復雜電路系統(tǒng)的完整Verilog HDL模型是由若干個Verilog HDL模塊構成的,每一個模塊又可以由若干個子模塊構成。其中有些模塊需要綜合成具體電路,而有些模塊只是與用戶所設計的模塊交互的現(xiàn)存電路或激勵信號源。利用Verilog HDL語言結構所提供的這種功能就可以構造一個模塊間的清晰層次結構來描述極其復雜的大型設計,并對所作設計的邏輯電路進行嚴格的驗證。   Verilog HDL行為描述語言作為一種結構化和過程性的語言,其語法結構非常適合于算法級和RTL級的模型設計。這種行為描述語言具有以下功能:   · 可描述順序執(zhí)行或并行執(zhí)行的程序結構。   · 用延遲表達式或事件表達式來明確地控制過程的啟動時間。   · 通過命名的事件來觸發(fā)其它過程里的激活行為或停止行為。   · 提供了條件、if-else、case、循環(huán)程序結構。   · 提供了可帶參數(shù)且非零延續(xù)時間的任務(task)程序結構。   · 提供了可定義新的操作符的函數(shù)結構(function)。   · 提供了用于建立表達式的算術運算符、邏輯運算符、位運算符。   · Verilog HDL語言作為一種結構化的語言也非常適合于門級和開關級的模型設計。因其結構化的特點又使它具有以下功能:   - 提供了完整的一套組合型原語(primitive);   - 提供了雙向通路和電阻器件的原語;   - 可建立MOS器件的電荷分享和電荷衰減動態(tài)模型。   Verilog HDL的構造性語句可以精確地建立信號的模型。這是因為在Verilog HDL中,提供了延遲和輸出強度的原語來建立精確程度很高的信號模型。信號值可以有不同的的強度,可以通過設定寬范圍的模糊值來降低不確定條件的影響。   Verilog HDL作為一種高級的硬件描述編程語言,有著類似C語言的風格。其中有許多語句如:if語句、case語句等和C語言中的對應語句十分相似。如果讀者已經(jīng)掌握C語言編程的基礎,那么學習Verilog HDL并不困難,我們只要對Verilog HDL某些語句的特殊方面著重理解,并加強上機練習就能很好地掌握它,利用它的強大功能來設計復雜的數(shù)字邏輯電路。下面我們將對Verilog HDL中的基本語法逐一加以介紹。

    標簽: Verilog_HDL

    上傳時間: 2014-12-04

    上傳用戶:cppersonal

  • XAPP1065 - 利用Spartan-6 FPGA設計擴頻時鐘發(fā)生器

      Consumer display applications commonly use high-speed LVDS interfaces to Transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.

    標簽: Spartan XAPP 1065 FPGA

    上傳時間: 2013-11-01

    上傳用戶:hjkhjk

  • XAPP708 -133MHz PCI-X到128MB DDR小型DIMM存儲器橋

      The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata Transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.

    標簽: PCI-X XAPP DIMM 708

    上傳時間: 2013-11-24

    上傳用戶:18707733937

  • SWIFT設計軟件工具

    SWIFT 提供的服務   1、接入服務   SWIFT的接入服務通過SWIFTAlliance的系列產(chǎn)品完成,包括:   (1) SWIFTAlliance Access and Entry:傳送FIN信息的接口軟件;   (2) SWIFTAlliance Gateway:接入SWIFTNet的窗口軟件;   (3) SWIFTAlliance Webstation:接入SWIFTNet的桌面接入軟件;   (4) File Transfer Interface:文件傳輸接口軟件,通過SWIFTNet FileAct是用戶方便的訪問其后臺辦公系統(tǒng)。   SWIFTNET Link軟件內嵌在SWIFTAlliance Gateway和SWIFTAlliance Webstation中,提供傳輸、標準化、安全和管理服務。連接后,它確保用戶可以用同一窗口多次訪問SWIFTNet,獲得不同服務。

    標簽: SWIFT 設計軟件

    上傳時間: 2013-12-22

    上傳用戶:sclyutian

  • OFELI is an object oriented library of C++ classes for development of finite element codes. Its main

    OFELI is an object oriented library of C++ classes for development of finite element codes. Its main features are : * Various storage schemes of matrices (dense, sparse, skyline). * Direct methods of solution of linear systems of equations as well as various combinations of iterative solvers and preconditioners. * Shape functions of most "popular" finite elements * Element arrays of most popular problems (Heat Transfer, Fluid Flow, Solid Mechanics, Electromagnetics, ...).

    標簽: development oriented classes element

    上傳時間: 2015-03-03

    上傳用戶:kbnswdifs

  • CBC下寫的串口編程

    CBC下寫的串口編程,API函數(shù)實例 I wish this site had been around when I was trying to figure out how to make serial communications work in Windows95. I, like many programmers, was hit with the double-whammy of having to learn Windows programming and Win95 serial comm programming at the same time. I found both tasks confusing at best. It was particularly frustrating because I had, over the years, written so much stuff (including lots of serial comm software) for the DOS environment and numerous embedded applications. Interrupt driven serial comm, DMA Transfer serial comm, TSR serial comm, C, assembler, various processors... you name it, it had written it. Yet, everything I knew seemed upside-down in the message-driven-callback world of Windows.

    標簽: CBC 串口編程

    上傳時間: 2014-06-20

    上傳用戶:cccole0605

  • Support is available from MIPS Technologies Inc. - problems should be addressed to support@mips.co

    Support is available from MIPS Technologies Inc. - problems should be addressed to support@mips.com。This product may be controlled for export purposes. You may not export, or Transfer for the purpose of reexport, any technical data received hereunder or the product produced by use of such technical data, including processes and services (the "product"), in violation of any U.S. or foreign regulation, treaty, Executive Order, law, statute, amendment or supplement thereto. Further, you may not export the product to any prohibited or embargoed country or to any denied, blocked, or designated person or entity as mentioned in any applicable U.S. or foreign regulation, treaty, Executive Order, law, statute, amendment or supplement thereto.

    標簽: Technologies available addressed problems

    上傳時間: 2014-01-24

    上傳用戶:二驅蚊器

  • a3load is 8051 firmware that can be used for uploading or downloading to EZ-USB RAM (internal or ex

    a3load is 8051 firmware that can be used for uploading or downloading to EZ-USB RAM (internal or external). It implements the vendor specific command bRequest = 0xA3. The address to download/upload to/from is specified in the wValue field of the SETUP packet and the length of the Transfer in the wLength field. The actual upload/download data is Transferred during the DATA stage of the SETUP Transfer. This firmware will function on all EZ-USB chips (EZ-USB, EZ-USB FX, FX2, FX2LP, FX1).

    標簽: downloading uploading firmware internal

    上傳時間: 2013-12-25

    上傳用戶:zhaiye

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