This application note contains a reference design consisting of HDL IP and Xilinx AdvancedConfiguration Environment (ACE) software utilities that give designers great flexibility increating in-system programming (ISP) solutions. In-system programming support allowsdesigners to revise existing designs, package the new bitstream programming files with theprovided software utilities, and Update the remote system through the JTAG interface using theEmbedded JTAG ACE Player.
The PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to Update the information contained herein.
This example shows how to Update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI).
The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT).
The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not Updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset.
If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on.
In this example the system is clocked by the HSE(8MHz).
This application note contains a reference design consisting of HDL IP and Xilinx AdvancedConfiguration Environment (ACE) software utilities that give designers great flexibility increating in-system programming (ISP) solutions. In-system programming support allowsdesigners to revise existing designs, package the new bitstream programming files with theprovided software utilities, and Update the remote system through the JTAG interface using theEmbedded JTAG ACE Player.
sheerdns is a master DNS server whose zone records are stored on a One-Record-Per-File bases. Because of this, it is the simplest of any DNS to configure, the easiest to Update, and the most efficient for networks that experience a lot of Updates (for example master servers for dynamic IP address ranges). You never have to restart it; any Updates are available immediately without having to notify the sheerdns process. 來源: http://freshmeat.net/projects/sheerdns/?topic_id=149 sheerdns是一個主DNS服務器，它的域記錄保存在一個One-Record-Per-File（每文件一個記錄）的庫中。因此，它是最簡單的DNS配制，最容易更新，對于有大量更新的網絡（如動態IP地址范圍的主服務器）來說它是最高效的。你不必重新啟動它，任何更新不用通知對應DNS進程就可以立即生效。
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