The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in VIRTEX™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVIRTEX-5 RocketIO™ GTP transceivers• Users can configure VIRTEX-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標簽： Transceiver VIRTEX Wizar GTP
上傳時間： 2013-10-20
上傳用戶：dave520l
UG203-VIRTEX-5 PCB設計指南
上傳時間： 2013-10-16
上傳用戶：helmos
UG190 VIRTEX-5 用戶指南
上傳時間： 2015-01-02
上傳用戶：xiaohanhaowei
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the VIRTEX-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上傳時間： 2013-12-25
上傳用戶：jkhjkh1982
xilinx VIRTEX architecture
標簽： architecture xilinx VIRTEX
上傳時間： 2015-02-06
上傳用戶：6546544
xilinx VIRTEX floorprint
標簽： floorprint xilinx VIRTEX
上傳時間： 2014-11-30
上傳用戶：cmc_68289287
VHDL編寫的PCI代碼,PCI2.2兼容,Xillinx VIRTEX與Spantan II 優化,33M主頻,32位寬度,全目標功能等.
標簽： PCI Spantan Xillinx VIRTEX
上傳時間： 2015-06-03
上傳用戶：大融融rr
SRL16是VIRTEX器件中的一個移位寄存器查找表。它有4個輸入用來選擇輸出序列的長度。使用XCV50-6器件實現，共占用5個Slice。用來生成gold碼。
上傳時間： 2015-06-16
上傳用戶：水中浮云
Xilinx的培訓教程的源碼 VIRTEX
上傳時間： 2015-08-31
上傳用戶：JIUSHICHEN
XAPP858 - 利用 VIRTEX-5 FPGA 實現的高性能 DDR2 SDRAM 接口數據采集 本應用指南描述了用于實現 667 Mbps（333 MHz）高性能 DDR2 SDRAM 接口的控制器和數據采集的技巧。 本數據采集技巧使用了輸入串行器/解串器（ISERDES）和輸出串行器/解串器（OSERDES）的功能。
上傳時間： 2014-01-19
上傳用戶：sk5201314
