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Verilog-A

the verilog code used to design a PIC uC

the verilog code used to design a PIC uC

標(biāo)簽： verilog design code used

上傳時(shí)間： 2014-01-19

上傳用戶：Thuan
a good book for learning verilog

a good book for learning verilog

標(biāo)簽： learning verilog good book

上傳時(shí)間： 2014-01-19

上傳用戶：標(biāo)點(diǎn)符號(hào)
is a test of a verilog implementation to do a oscilloscope with dual-port RAM

is a test of a verilog implementation to do a oscilloscope with dual-port RAM

標(biāo)簽： implementation oscilloscope dual-port verilog

上傳時(shí)間： 2014-01-03

上傳用戶：15736969615
code for fpga is written in verilog,cardinality is a thing which is very important

code for fpga is written in verilog,cardinality is a thing which is very important

標(biāo)簽： cardinality important is written

上傳時(shí)間： 2013-12-20

上傳用戶：moerwang
This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM

This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master

標(biāo)簽： code oversampled implement include

上傳時(shí)間： 2013-12-13

上傳用戶：leixinzhuo
this is a code of AMBA AHB master protocol in verilog

this is a code of AMBA AHB master protocol in verilog

標(biāo)簽： protocol verilog master this

上傳時(shí)間： 2017-09-10

上傳用戶：冇尾飛鉈
Verilog, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer.

Verilog, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version minimig-j used on the Minimig fpga board.

標(biāo)簽： implementation the computer Verilog

上傳時(shí)間： 2017-09-24

上傳用戶：xauthu
介紹配置曼徹斯特編碼器譯碼器的VHDL和Verilog源代碼

This application note provides a functional des cription of VHDL and Verilog source code for a

標(biāo)簽： Verilog VHDL 曼徹斯特編碼器

上傳時(shí)間： 2013-07-04

上傳用戶：李夢晗
《Verilog HDL 硬件描述語言》

·詳細(xì)說明：正式出版物《Verilog HDL 硬件描述語言》一書的精美 PDF 電子版。- Official publication Verilog HDL Hardware Description Language a book fine PDF electron version.目錄譯者序前言第1章簡介&n

標(biāo)簽： nbsp Verilog HDL 硬件描述語言

上傳時(shí)間： 2013-07-02

上傳用戶：6404552
采用FPGA模擬高動(dòng)態(tài)GPS信號(hào)源中的C／A碼產(chǎn)生器

本文：采用了FPGA方法來模擬高動(dòng)態(tài)(Global Position System GPS)信號(hào)源中的C／A碼產(chǎn)生器。C／A碼在GPS中實(shí)現(xiàn)分址、衛(wèi)星信號(hào)粗捕和精碼(P碼)引導(dǎo)捕獲起著重要的作用，通過硬件描述語言VERILOG在ISE中實(shí)現(xiàn)電路生成，采用MODELSIM、SYNPLIFY工具分別進(jìn)行仿真和綜合。

標(biāo)簽： FPGA GPS 模擬動(dòng)態(tài)

上傳時(shí)間： 2013-08-31

上傳用戶：pwcsoft