Wireless networking is undergoing a transformation from what has been primarily a medium for supporting voice traffic between telephones, into what is increasingly becoming a medium for supporting traffic among a variety of digital devices transmitting media of many types (voice, data, images, video. etc.) Wireline networking underwent a similar transformation in the 1990s, which led to an enormous build-up in the capacity of such networks, primarily through the addition of new optical fiber, switches and other infrastructure.
標(biāo)簽： Multiusers Detection Wireless Networks
上傳時(shí)間： 2020-06-01
上傳用戶：shancjb
The advent of modern wireless devices, such as smart phones and MID 1 terminals, has revolutionized the way people think of personal connectivity. Such devices encompass multiple applications ranging from voice and video to high-speed data transfer via wireless networks. The voracious appetite of twenty-first century users for supporting more wireless applications on a single device is ever increasing. These devices employ multiple radios and modems that cover multiple frequency bands and multiple standards with a manifold of wireless applications often running simultaneously.
標(biāo)簽： Architectures Wireless Receiver Design and
上傳時(shí)間： 2020-06-01
上傳用戶：shancjb
Mobile radio communications are evolving from pure telephony systems to multimedia platforms offering a variety of services ranging from simple file transfers and audio and video streaming, to interactive applications and positioning tasks. Naturally, these services have different constraints concerning data rate, delay, and reliability (quality-of-service (QoS)). Hence, future mobile radio systems have to provide a large flexibility and scal- ability to match these heterogeneous requirements.
標(biāo)簽： Communications Wireless Channels MIMO over
上傳時(shí)間： 2020-06-01
上傳用戶：shancjb
Wirelesscommunications,especiallyinitsmobileform,hasbroughtusthefreedomofmobility andhaschangedthelifestylesofmodernpeople.Waitingatafixedlocationtoreceiveormakea phone call, or sitting in front of a personal computer to send an e-mail or download a video program, has become an old story. Nowadays it is commonplace for people to talk over a cell phonewhilewalkingonthestreet,ortodownloadandwatchamoviewhiletravelingonatrain. Thisisthebenefitmadeavailabletousbythesuccessfulevolutionofwirelesscommunications over three generations, with the fourth generation being under way.
標(biāo)簽： Communications Management Wireless Resource
上傳時(shí)間： 2020-06-01
上傳用戶：shancjb
Although state of the art in many typical machine learning tasks, deep learning algorithmsareverycostly interms ofenergyconsumption,duetotheirlargeamount of required computations and huge model sizes. Because of this, deep learning applications on battery-constrained wearables have only been possible through wireless connections with a resourceful cloud. This setup has several drawbacks. First, there are privacy concerns. Cloud computing requires users to share their raw data—images, video, locations, speech—with a remote system. Most users are not willing to do this. Second, the cloud-setup requires users to be connected all the time, which is unfeasible given current cellular coverage. Furthermore, real-time applications require low latency connections, which cannot be guaranteed using the current communication infrastructure. Finally, wireless connections are very inefficient—requiringtoo much energyper transferredbit for real-time data transfer on energy-constrained platforms.
標(biāo)簽： Embedded_Deep_Learning Algorithms
上傳時(shí)間： 2020-06-10
上傳用戶：shancjb
基于界面操作的人臉心率檢測的代碼，通過攝像頭實(shí)時(shí)采集人視頻，并計(jì)算心率(Face the heart rate detection interface operation based on the code, through real-time acquisition one camera video, and rate)
上傳時(shí)間： 2021-02-24
上傳用戶：
基于FPGA設(shè)計(jì)的字符VGA LCD顯示實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說明,通過字符轉(zhuǎn)換工具將字符轉(zhuǎn)換為 8 進(jìn)制 mif 文件存放到單端口的 ROM IP 核中，再從ROM 中把轉(zhuǎn)換后的數(shù)據(jù)讀取出來顯示到 VGA 上，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上傳時(shí)間： 2021-12-18
上傳用戶：
基于FPGA設(shè)計(jì)的vga顯示測試實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說明，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r = video_r[7:3]; //discard low bit dataassign vga_out_g = video_g[7:2]; //discard low bit dataassign vga_out_b = video_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule
標(biāo)簽： fpga vga顯示 verilog quartus
上傳時(shí)間： 2021-12-19
上傳用戶：kingwide
ADC模數(shù)轉(zhuǎn)換器件Altium Designer AD原理圖庫元件庫SV text has been written to file : 4.4 - ADC模數(shù)轉(zhuǎn)換器件.csvLibrary Component Count : 29Name Description----------------------------------------------------------------------------------------------------ADC0800 National 8-Bit Analog to Digital ConverterADC0809 ADC0831 ADCADC0832 ADC8 Generic 8-Bit A/D ConverterCLC532 High-Speed 2:1 Analog MultiplexerCS5511 National 16-Bit Analog to Digital ConverterDAC8 Generic 8-Bit D/A ConverterEL1501 Differential line Driver/ReceiverEL2082 Current-Mode MultiplierEL4083 Current Mode Four Quadrant MultiplierEL4089 DC Restored Video AmplifierEL4094 Video Gain Control/FaderEL4095 Video Gain Contol/Fader/MultiplexerICL7106 LMC6953_NSC PCI Local Bus Power SupervisorMAX4147 300MHz, Low-Power, High-Output-Current, Differential Line DriverMAX4158 350MHz 2-Channel Video Multiplexer-AmplifierMAX4159 350MHz 2-Channel Video Multiplexer-AmplifierMAX4258 250MHz, 2-Channel Video Multiplexer-AmplifierMAX4259 250MHz 2-Channel Video Multiplexer-AmplifierMAX951 Ultra-Low-Power, Single-Supply Op Amp + Comparator + ReferenceMAX952 Ultra-Low-Power, Single-Supply Op Amp + Comparator + ReferenceMC1496 Balanced Modulator/DemodulatorPLL100k Generic Phase Locked LoopPLL10k Generic Phase Locked LoopPLL5k Generic Phase Locked LoopPLLx Generic Phase Locked Loop水位計(jì)
標(biāo)簽： adc 模數(shù)轉(zhuǎn)換 altium designer
上傳時(shí)間： 2022-03-13
上傳用戶：
MS9123 是一款單芯片 USB 投屏器，內(nèi)部集成了 USB2.0 控制器和數(shù)據(jù)收發(fā)模塊、視頻 DAC 和音 視頻處理模塊，MS9123 可以通過 USB 接口顯示或者擴(kuò)展 PC、智能手機(jī)、平板電腦的顯示信息到 更大尺寸的顯示設(shè)備上，支持 CVBS、S-Video 視頻接口
上傳時(shí)間： 2022-03-25
上傳用戶：
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