keil 使用筆記:在Memory窗口上輸入address_type:address才能看到正確地址的變量debug～perfermance analyzer加入要察看的模塊名稱(chēng)，然后view～perfermance analyzer window 可以察看各個(gè)模塊運(yùn)行時(shí)間①Display address_type:address B:Bit address C:Code Memory Bx:Code Bank D D：80H 命令可以查看特殊寄存器 data D I：0 命令可以查看內(nèi)部RAM數(shù)據(jù)iData； D X：0 命令可以查看外部RAM數(shù)據(jù)xData； ②R1 //顯示R1 register ~R1 //顯示變量R1 R1 = R7 //對(duì)寄存器Rx操作R1 = --R7 R1 = 0x20 ③main //顯示main()的開(kāi)始地址d main //顯示main()的代碼④向RAM.ROM中寫(xiě)數(shù)據(jù)Enter data_type address_type:address expr,expr.... data_type:int char double float long E char data:0x20 1,2,3,4 //向data區(qū)0x20開(kāi)始的地址寫(xiě)1,2,3,4 變量放在RAM的30H，要把定義放在main前面!另外特別注意，內(nèi)部RAM通常供C程序存放中間變量等，所以一定要看看編譯后的程序中是否存在存儲(chǔ)單元沖突的情況，比如如果程序中 使用了別的寄存器組的話，08-1FH單元就不能用了unsigned long data i _at_ 0x30
上傳時(shí)間： 2013-11-05
上傳用戶：dongqiangqiang
這一顆，我們學(xué)習(xí)如何讓跑馬燈自動(dòng)按照我們預(yù)定的順序進(jìn)行。這種控制在工控場(chǎng)合經(jīng)常用到。這個(gè)程序里，我們預(yù)先定義了一個(gè)變化的順序speedcode，每跑一圈燈就根據(jù)預(yù)定設(shè)置的表格數(shù)據(jù)來(lái)決定下一圈的跑馬速度。這樣我們就實(shí)現(xiàn)了按照預(yù)定的順序自動(dòng)變化運(yùn)行。請(qǐng)看代碼：-----------------------------------#define uchar unsigned char //定義一下方便使用#define uint unsigned int#define ulong unsigned long#include <reg52.h> //包括一個(gè)52 標(biāo)準(zhǔn)內(nèi)核的頭文件sbit P10 = P1^0; //頭文件中沒(méi)有定義的IO 就要自己來(lái)定義了sbit P11 = P1^1;sbit P12 = P1^2;sbit P13 = P1^3;bit ldelay=0; //長(zhǎng)定時(shí)溢出標(biāo)記,預(yù)置是0uchar speed=10; //設(shè)置一個(gè)變量保存跑馬燈的移動(dòng)速度uchar code speedcode[10]={3,1,5,12,3,20,2,10,1,4}; //10 個(gè)預(yù)定義的速度char code dx516[3] _at_ 0x003b;//這是為了仿真設(shè)置的//可編程自動(dòng)控制跑馬燈void main(void) // 主程序{uchar code ledp[4]={0xfe,0xfd,0xfb,0xf7};//預(yù)定的寫(xiě)入P1 的值uchar ledi; //用來(lái)指示顯示順序uchar i;RCAP2H =0x10; //賦T2 的預(yù)置值0x1000，溢出30 次就是1 秒鐘RCAP2L =0x00;TR2=1; //啟動(dòng)定時(shí)器ET2=1; //打開(kāi)定時(shí)器2 中斷EA=1; //打開(kāi)總中斷
標(biāo)簽： 可編程 自動(dòng)控制 控制 跑馬燈
上傳時(shí)間： 2013-11-20
上傳用戶：ming529
單片機(jī)指令系統(tǒng) 3.1 MCS－51指令簡(jiǎn)介 3.2 指令系統(tǒng) 3.1 MCS－51指令簡(jiǎn)介 二、MCS－51系列單片機(jī)指令系統(tǒng)分類(lèi) 按尋址方式分為以下七種：按功能分為以下四種： 1、立即立即尋址 1、數(shù)據(jù)傳送指令位操 2、直接尋址 2、算術(shù)運(yùn)算指令 3、寄存器尋址 3、邏輯運(yùn)算指令 4、寄存器間接尋址指令 4、控制轉(zhuǎn)移類(lèi)指令 5、相對(duì)尋址 5、位操作指令 6、變址尋址 7、位尋址 三、尋址方式 3、寄存器間接尋址 MOV A, @R1 操作數(shù)是通過(guò)寄存器間接得到的。 4、立即尋址 MOV A, #40H 操作數(shù)在指令中直接給出。 5、基址寄存器加變址寄存器尋址 以DPTR或PC為基址寄存器，以A為變址寄存器， 以兩者相加形成的16位地址為操作數(shù)的地址。 MOVC A, @A+DPTR MOVC A, @A+PC 四、指令中常用符號(hào)說(shuō)明 Rn——當(dāng)前寄存器區(qū)的8個(gè)工作寄存器R0～R7(n＝0～7)； Ri——當(dāng)前寄存器區(qū)可作地址寄存器的2個(gè)工作寄存器R0和R1(i＝0，1)； direct——8位內(nèi)部數(shù)據(jù)存儲(chǔ)器單元的地址及特殊功能寄存器的地址； #data——表示8位常數(shù)（立即數(shù)）； #datal6——表示16位常數(shù)； add 16——表示16位地址； addrll——表示11位地址； rel——8位帶符號(hào)的地址偏移量； bit——表示位地址； @——間接尋址寄存器或基址寄存器的前綴； ( )——表示括號(hào)中單元的內(nèi)容 (( ))——表示間接尋址的內(nèi)容； 五、MCS－51指令簡(jiǎn)介 1. 以累加器A為目的操作數(shù)的指令 2. 以Rn為目的操作數(shù)的指令 3. 以直接地址為目的操作數(shù)的指令 4. 以寄存器間接地址為目的操作數(shù)指令 應(yīng)用舉例1 8段數(shù)碼管顯示 應(yīng)用舉例2 3.2 指令系統(tǒng) 2、堆棧操作指令 3. 累加器A與外部數(shù)據(jù)傳輸指令 4. 查表指令 MOVC A, @A+PC 例子： 5. 字節(jié)交換指令 6. 半字節(jié)交換指令 二、算術(shù)操作類(lèi)指令 PSW寄存器 2. 帶進(jìn)位加法指令 3. 加1指令 4. 十進(jìn)制調(diào)整指令 5. 帶借位減法指令（Subtraction） 6. 減1指令（Decrease） 7. 乘法指令（Multiplication） 8. 除法指令（Division） 三、邏輯運(yùn)算指令 1. 簡(jiǎn)單邏輯操作指令 2. 循環(huán)指令 帶進(jìn)位左循環(huán)指令（Rotate Accumulator Left through Carry flag） 右循環(huán)指令（Rotate Accumulator Right） 帶進(jìn)位右循環(huán)指令（Rotate A Right with C） 3. 邏輯與指令 4. 邏輯或指令 5. 邏輯異或指令 四、控制轉(zhuǎn)移類(lèi)指令 1. 跳轉(zhuǎn)指令 相對(duì)轉(zhuǎn)移指令 SJMP rel PC←(PC)+2 PC←(PC)+rel 程序中標(biāo)號(hào)與地址之間的關(guān)系 2. 條件轉(zhuǎn)移指令 3. 比較不相等轉(zhuǎn)移指令 4. 減 1 不為 0 轉(zhuǎn)移指令 5. 調(diào)用子程序指令 7. 中斷返回指令 五、位操作指令 1. 數(shù)據(jù)位傳送指令 2. 位變量邏輯指令 3. 條件轉(zhuǎn)移類(lèi)指令
標(biāo)簽： 單片機(jī) 指令系統(tǒng)
上傳時(shí)間： 2013-10-27
上傳用戶：xuanjie
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標(biāo)簽： synchronous Emulating serial
上傳時(shí)間： 2014-01-31
上傳用戶：z1191176801
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
標(biāo)簽： Bridge Memory Contr MPC
上傳時(shí)間： 2013-10-08
上傳用戶：18711024007
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽： Signal Input Fall Rise
上傳時(shí)間： 2013-10-23
上傳用戶：copu
The P90CL301 is a highly integrated 16/32 bit micro-controller especially suitable for applications requiring lowvoltage and low power consumption. It is fully software compatible with the 68000. Furthermore, it provides bothstandard as well as advanced peripheral functions on-chip.One of these peripheral functions is the I2C bus. This report describes worked-out driver software (written in C) toprogram the P90CL301 I2C interface. It also contains interface software routines offering the user a quick start inwriting a complete I2C system application.
上傳時(shí)間： 2014-01-06
上傳用戶：氣溫達(dá)上千萬(wàn)的
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
標(biāo)簽： C16x 微控制器 輸入信號(hào) 時(shí)序圖
上傳時(shí)間： 2014-04-02
上傳用戶：han_zh
This application note demonstrates how to write an Inter Integrated Circuit bus driver (I2C) for the XA-S3 16-bitMicrocontroller from Philips Semiconductors.Not only the driver software is given. This note also contains a set of (example) interface routines and a smalldemo application program. All together it offers the user a quick start in writing a complete I2C system applicationwith the PXAS3x.The driver routines support interrupt driven single master transfers. Furthermore, the routines are suitable foruse in conjunction with real time operating systems.
標(biāo)簽： software driver XA-S I2C
上傳時(shí)間： 2013-11-02
上傳用戶：zw380105939
The XA-S3 is a member of Philips Semiconductors’ XA (eXtended Architecture) family of high performance 16-bit single-chip Microcontrollers. The XA-S3 combines many powerful peripherals on one chip. Therefore, it is suited for general multipurpose high performance embedded control functions.One of the on-chip peripherals is the I2C bus interface. This report describes worked-out driver software (written in C) to program / use the I2C interface of the XA-S3. The driver software, together with a demo program and interface software routines offer the user a quick start in writing a complete I2C - XAS3 system application.
上傳時(shí)間： 2013-11-10
上傳用戶：liaofamous
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
<strike id="gwsym"></strike>
<strike id="gwsym"></strike>