ALLEGRO15.X學習與的用（下）
上傳時間： 2013-06-28
上傳用戶：1136815862
Orcad 使用
標簽： Orcad
上傳時間： 2013-06-28
上傳用戶：lepoke
stc 單片機ISP程序
上傳時間： 2013-09-05
上傳用戶：a471778
著名的游戲開發庫Allegro4.2.0 for DELPHI.rar
上傳時間： 2013-09-06
上傳用戶：海陸空653
cadence_virtuoso軟件新手入門教材，用戶手冊。
標簽： cadence_virtuoso 軟件 入門教
上傳時間： 2013-09-09
上傳用戶：hoperingcong
* DESCRIPTION: DDS design BY PLD DEVICES.\r\n *\r\n * AUTHOR: Sun Yu\r\n *\r\n * HISTORY: 12/06/2002 \r\n *
標簽： DESCRIPTION DEVICES design DDS
上傳時間： 2013-09-09
上傳用戶：jokey075
上傳時間： 2013-11-03
上傳用戶：taox
allegro16.3教程1
上傳時間： 2013-11-16
上傳用戶：urgdil
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標簽： Efficient Verilog Digital Coding
上傳時間： 2013-11-22
上傳用戶：han_zh
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上傳時間： 2014-12-23
上傳用戶：xinhaoshan2016
