it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
標簽：
synthesize
simulator
modelsim
verilog
上傳時間：
2014-06-26
上傳用戶：zhuyibin
