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configured

This temp directory is used by the JVM for temporary file storage. The JVM is configured to use thi

This temp directory is used by the JVM for temporary file storage. The JVM is configured to use this as its java.io.tmpdir in the catalina.sh and catalina.bat scripts.

標簽： configured JVM directory temporary

上傳時間： 2016-04-15

上傳用戶：363186
IAR project for MSP430 and uC/OS. All configured to start filling with tasks.

IAR project for MSP430 and uC/OS. All configured to start filling with tasks.

標簽： configured project filling start

上傳時間： 2014-01-18

上傳用戶：sy_jiadeyi
This example application requires several components to be setup and configured before running. It

This example application requires several components to be setup and configured before running. It is assumed that you understand how to setup a Web application and add the components below.

標簽： application components configured requires

上傳時間： 2016-12-02

上傳用戶：大三三
This program requires the DSP2833x header files. // // As supplied, this project is configured

This program requires the DSP2833x header files. // // As supplied, this project is configured for "boot to SARAM" // operation. The 2833x Boot Mode table is shown below. // For information on configuring the boot mode of an eZdsp, // please refer to the documentation included with the eZdsp,

標簽： configured requires supplied program

上傳時間： 2014-01-10

上傳用戶：lixinxiang
效率85％的12v轉5v降壓轉換器

This application note describes how the NCP3063 can be configured as a buck controller to drive an e

標簽： 12v 效率降壓轉換器

上傳時間： 2013-05-28

上傳用戶：mslj2008
LTC6994參考設計及PCB布線規則

Demonstration circuit 1562A is an engineering toolto design and evaluate the LTC699X-X family ofTimerBlox circuits. The center section of the boardcontains a pre-configured TimerBlox function.DC1562A comes in twelve timing function variationsas outlined in Table 1.Surrounding the center board is a ”playground”prototyping area. The prototyping area has padsfor Dip-8, S8, MS8, or S6 packages with breadboarding connections to each pin and two convenientpower buses and ground bus surrounding theentire area. This area is for conditioning signals tocontrol the timer function and for adding loads controlled in time.

標簽： 6994 LTC PCB 參考設計

上傳時間： 2013-10-18

上傳用戶：如果你也聽說
CAT93C46 器件數據手冊

The CAT93C46 is a 1 kb Serial EEPROM memory device which isconfigured as either 64 registers of 16 bits (ORG pin at VCC) or 128registers of 8 bits (ORG pin at GND). Each register can be written (orread) serially by using the DI (or DO) pin. The CAT93C46 features aself−timed internal write with auto−clear. On−chip Power−On Resetcircuit protects the internal logic against powering up in the wrongstate.

標簽： CAT 93C C46 93

上傳時間： 2013-11-20

上傳用戶：ynzfm
XAPP694-從配置PROM讀取用戶數據

This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.

標簽： XAPP PROM 694 讀取

上傳時間： 2013-11-11

上傳用戶：zhouli
XAPP719 -利用USR_ACCESS寄存器實現PowerPC高速緩存配置

The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a series of 32-bitwords.

標簽： USR_ACCESS PowerPC XAPP 719

上傳時間： 2013-11-13

上傳用戶：我累個乖乖
Virtex-5 GTP Transceiver Wizar

The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts

標簽： Transceiver Virtex Wizar GTP

上傳時間： 2013-10-23

上傳用戶：leyesome

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configured

This temp directory is used by the JVM for temporary file storage. The JVM is configured to use thi

IAR project for MSP430 and uC/OS. All configured to start filling with tasks.

This example application requires several components to be setup and configured before running. It

This program requires the DSP2833x header files. // // As supplied, this project is configured

效率85％的12v轉5v降壓轉換器

LTC6994參考設計及PCB布線規則

CAT93C46 器件數據手冊

XAPP694-從配置PROM讀取用戶數據

XAPP719 -利用USR_ACCESS寄存器實現PowerPC高速緩存配置

Virtex-5 GTP Transceiver Wizar